Method to reduce the common-mode EMI of a full bridge converter using sampling common-mode feedback
AssigneeAnalog Devices International Unlimited Company
InventorsCiaran Brennan, Brian K. Jadus, Keith W. Bennett
Life of this patent
Estimating the term…
Abstract
A switched power circuit to control a common-mode signal. The switched power circuit includes a first switch and a second switch configured to generate switch mode voltage between a first node and a second node. The switched power circuit further includes a feedback circuit that is configured to detect common-mode voltage generated between the first node and the second node by a first signal generated by the first switch and a second signal generated by the second switch, and incrementally adjust a timing parameter of the first signal to adjust the common-mode signal.
Claims15
A switch mode power circuit to control a common-mode signal, the switch mode power circuit comprising:
- a first switch and a second switch configured to establish switch mode voltage or current between a first node and a second node;
- and
- a feedback circuit configured to:
- detect common-mode voltage signal generated at the first node and the second node by a first signal generated by the first switch and a second signal generated by the second switch;
- and
- incrementally adjust a timing parameter of the first signal to adjust the common-mode voltage signal, wherein the timing parameter of the first signal includes one of a slew rate or a delay of the first signal;
- and
- wherein the feedback circuit comprises a memory circuit, including a binary counter, to store a value to control the timing parameter of the first signal, and an evaluation circuit, including a comparator, to incrementally update the stored value based on the detected common-mode voltage signal, and wherein the feedback circuit is configured to:
- (1) determine, by the comparator at an indicated time in a switching cycle of the switch mode power circuit, a difference between the first signal and the second signal;
- and (2) increment or decrement a count stored in the binary counter, based on the determined difference.
A device having a circuit for reducing common-mode electromagnetic interference, the circuit comprising:
- a first inductor having a first terminal and a second terminal;
- a second inductor coupled to a power supply, the second inductor configured to induce a voltage or current in the first inductor;
- a first switch circuit coupled to the first terminal at a first node and a second switch circuit coupled to the second terminal at a second node, wherein the first switch circuit is a pull-down circuit that is configured to drive the first node to a negative voltage relative to the second node and the second switch circuit is a pull-up circuit that is configured to drive the second node to a positive voltage relative to the first node;
- a driver circuit configured to control a switching characteristic of the first switch circuit;
- and
- a feedback circuit coupled to the first node and the second node, the feedback circuit comprising:
- a storage circuit, including a binary counter circuit, that is configured to provide an input to the driver circuit;
- and
- a comparator circuit that is configured to incrementally update the binary counter circuit based on a difference between a first signal at the first node and a second signal at the second node to reduce a common mode voltage in the first signal and the second signal.
A method for reducing common-mode electromagnetic interference in a power converter, the method comprising:
- detecting a common-mode voltage signal across an inductive element during actuation of a switching circuit that is configured to drive the inductive element, the detecting the common-mode voltage signal including determining, by a comparator at an indicated time in a switching cycle of the switching circuit, a difference between a first signal at a first terminal of the inductive element and a second signal at a second terminal of the inductive element;
- determining, based on the determined difference, an update direction to update a stored value in a binary counter of a memory circuit that is used to determine a timing parameter of the switching circuit, wherein the timing parameter of the first signal includes one of a slew rate or a delay of the first signal;
- incrementally updating the stored value based on the determined update direction, including by incrementing or decrementing a count stored in the binary counter of the memory circuit based on the determined difference;
- and
- adjusting the timing parameter based on the updated stored value.
Dependencies are inferred from the claim text.