Half-bridge electronic device comprising two systems for optimizing dead-time between the switching operations of a high level switch and of a low level switch

A method, comprising:

• synchronizing an alternate activation of a low-side switch and a high-side switch in a half-bridge electronic device, the synchronizing including:
• deactivating the low-side switch when a first control signal passes to a state 0;
• interpreting a variation along a rising edge of a voltage at a central point to generate a second synchronization signal;
• activating the high-side switch by a second activation/deactivation signal resulting directly from the combining the second synchronization signal with a second control signal in an AND type logic gate;
• deactivating the high-side switch when the second control signal passes to the state 0;
• interpreting a variation along a falling edge of the voltage at the central point to generate a first synchronization signal separate from the second synchronization signal;
• activating the low-side switch by a first activation/deactivation signal resulting directly from combining the first synchronization signal with the first control signal in an AND type logic gate;
• generating a first transient current dependent on variations in the voltage at the central point with a first capacitive element in a first detection circuit in the first synchronization signal;
• and
• measuring a voltage proportional to the first transient current with a first diode and a first shunt resistor current in series with the first capacitive element.

A device comprising:

• a half-bridge electronic circuit that includes:
• a first switch that is configured to receive a first activation/deactivation signal;
• a second switch coupled in series with the first switch at a central point, the second switch configured to receive a second activation/deactivation signal;
• a first synchronization system that includes:
• a first capacitive element configured to generate a first transient current dependent on variations in a voltage at the central point;
• a first diode and a first resistor coupled to the first capacitive element, the first diode and first resistor configured to measure a voltage proportional to the first transient current, the first synchronization system configured to interpret a variation in the voltage along a falling edge and to generate a first synchronization signal;
• a second synchronization system configured to generate a second synchronization signal;
• a first AND-type logic gate configured to combine the first synchronization signal with a first control signal to generate the first activation/deactivation signal;
• and
• a second AND-type logic gate configured to combine the second synchronization signal with a second control signal to generate the second activation/deactivation signal.