Shoot-through current limiting circuit

A circuit, comprising:

• a logic circuit having an output, the logic circuit configured to assert a ship mode request signal as a specific logical value to request entry of the circuit into a ship mode;
• a first comparator having a first input coupled to an input voltage pin, a second input configured to receive an input voltage under voltage lockout (VINUVLO) threshold value, and an output, the first comparator configured to assert a first comparison signal as the specific logical value when an input voltage is less than the VINUVLO threshold value;
• a second comparator having a first input coupled to a power-middle (PMID) pin, a second input coupled to a battery pin, and an output, the second comparator configured to assert a second comparison signal as the specific logical value when a voltage at the PMID pin is less than a battery voltage at the battery pin;
• and
• an AND logic circuit having a first input coupled to the output of the logic circuit, a second input coupled to the output of the first comparator, a third input coupled to the output of the second comparator, and an output adapted to be coupled to an input of a field-effect transistor (FET) control circuit, the AND logic circuit configured to assert a ship mode enable signal as the specific logical value when each of the ship mode request signal, the first comparison signal and the second comparison signal is the specific logical value.

A system, comprising:

• a first transistor having a first control terminal and first and second current terminals, wherein the first current terminal is coupled to an input voltage terminal;
• a second transistor having a second control terminal and third and fourth current terminals, wherein the fourth current terminal is coupled to the second current terminal;
• a transistor control circuit having a transistor control input and first and second transistor control outputs, wherein the first and second transistor control outputs are coupled to the first and second control terminals, respectively;
• a control circuit, comprising:
• a first logic circuit configured to provide a ship mode request signal at a first logic output;
• a first comparator having a first comparator output and first and second comparator inputs, wherein the first comparator input is coupled to the first current terminal, and the second comparator input is coupled to a threshold terminal;
• a second comparator having a second comparator output and third and fourth comparator inputs, wherein the third comparator input is coupled to the third current terminal, and the fourth comparator input is coupled to a battery terminal;
• and
• a second logic circuit having a second logic output and first, second and third logic inputs, wherein the first logic input is coupled to the first logic output, the second logic input is coupled to the first comparator output, the third logic input is coupled to the second comparator output, and the second logic output is coupled to the transistor control input;
• and
• a battery coupled to the battery terminal;
• wherein the second logic circuit is configured to provide a ship mode enable signal at the second logic output responsive to a signal at the first comparator output and a signal at the second comparator output each being asserted.