Non-volatile memory cell and non-volatile memory

A semiconductor device, comprising:

• a substrate having a fin extending along a first direction;
• a plurality of insulators located over the substrate, wherein the fin is located between the plurality of insulators;
• a floating gate, over the fin and the plurality of insulators, wherein the floating gate extends along a second direction different from the first direction;
• a first gate structure, over the substrate and located at a first side of the fin;
• and
• a second gate structure, over the substrate and comprising at least two conductive structures connected to one another and located at a second side of the fin, wherein the first side is opposite to the second side.

A semiconductor device, comprising:

• a plurality of non-volatile memory cells, arranged into an array form and each comprising:
• a substrate having a fin, the fin comprising a source region and a drain region;
• a plurality of insulators located over the substrate, wherein the fin is located between the plurality of insulators;
• a floating gate, over the fin and the plurality of insulators, the floating gate and the fin extending in different directions, and the drain region and the source region being at two opposite sides of the floating gate;
• a first gate structure, over the substrate and located at a first side of the fin;
• and
• a second gate structure, over the substrate and comprising at least two conductive structures connected to one another and located at a second side of the fin, wherein the first side is opposite to the second side;
• a first conductive line, located over the plurality of non-volatile memory cells and extending along a first direction, wherein the first conductive line is electrically connected to source regions of the plurality of non-volatile memory cells located at two opposite sides of the first conductive line;
• a second conductive line, located over the plurality of non-volatile memory cells and extending along a second direction, wherein the second conductive line is electrically connected to drain regions of the plurality of non-volatile memory cells located at one side of the second conductive line, and the second direction is perpendicular to the first direction;
• and
• a third conductive line, located over the plurality of non-volatile memory cells and extending along the first direction, wherein the third conductive line is electrically connected to control gates of the plurality of non-volatile memory cells located at one side of the third conductive line, wherein at least one row or one column of non-volatile memory cells of the plurality of non-volatile memory cells is located between the first conductive line and the third conductive line.