Channel layer formation for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)

A computing device, comprising:

• a processor;
• and
• a memory device coupled to the processor, wherein the memory device or the processor includes a transistor comprising:
• isolation areas above a substrate to form a trench between the isolation areas;
• a first buffer layer over the substrate, in contact with the substrate, and within the trench;
• a second buffer layer within the trench over the first buffer layer, in contact with the first buffer layer;
• a channel area above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, wherein the channel area includes an III-V material;
• a high-k gate dielectric layer above the first buffer layer and completely around the channel area;
• a gate electrode above the first buffer layer, completely around the high-k gate dielectric layer, and completely around the channel area, wherein the gate electrode has a bottommost surface below the channel area, the bottommost surface of the gate electrode below a top of the second buffer layer and above a bottom of the first buffer layer;
• the source area above the second buffer layer, in direct contact with the second buffer layer, and adjacent to a first end of the channel area;
• and
• the drain area above the second buffer layer, in direct contact with the second buffer layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area.

A semiconductor device, comprising:

• isolation areas above a substrate to form a trench between the isolation areas;
• a first buffer layer over the substrate, in contact with the substrate, and within the trench;
• a second buffer layer within the trench over the first buffer layer, in contact with the first buffer layer;
• a channel area above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, wherein the channel area includes an III-V material;
• a high-k gate dielectric layer above the first buffer layer and completely around the channel area;
• a gate electrode above the first buffer layer, completely around the high-k gate dielectric layer, and completely around the channel area, wherein the gate electrode has a bottommost surface below the channel area, the bottommost surface of the gate electrode below a top of the second buffer layer and above a bottom of the first buffer layer;
• the source area above the second buffer layer, in contact with the second buffer layer, and adjacent to a first end of the channel area;
• and
• the drain area above the second buffer layer, in contact with the second buffer layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area, wherein the second buffer layer is coplanar with a surface of the isolation areas, while the channel area, the source area, and the drain area are above the surface of the isolation areas.