Memory cell comprising a transistor that comprises a pair of insulator-material regions and an array of transistors
AssigneeMicron Technology, Inc.
InventorDurai Vishak Nirmal Ramaswamy
Life of this patent
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Abstract
A transistor comprises a pair of source/drain regions having a channel there-between. A transistor gate construction is operatively proximate the channel. The channel comprises Si1-yGey, where “y” is from 0 to 0.6. At least a portion of each of the source/drain regions comprises Si1-xGex, where “x” is from 0.5 to 1. Other embodiments, including methods, are disclosed.
Claims21
An array of transistors, the transistors individually comprising:
- a pair of source/drain regions having a channel there-between;
- a transistor gate construction operatively proximate the channel;
- the channel comprising Si1-yGey, where “y” is from 0 to 0.6;
- and
- at least a portion of each of the source/drain regions comprising Si1-xGex, where “x” is from 0.5 to 1, neither of the portions nor the Si1-xGex therein is directly against the channel, each of the source/drain regions comprises the Si1-yGey and which is directly against the Si1-yGey of the channel, “y” being greater than 0.
An array of transistors, the transistors individually comprising:
- a pair of solid source/drain regions having a channel there-between;
- a transistor gate construction operatively proximate the channel;
- the channel comprising a direction of current flow there-through between the pair of solid source/drain regions;
- and
- a pair of insulator-material regions in the channel that are each elongated orthogonal to the current-flow direction, are each extending completely through the channel orthogonal to the current-flow direction, and are each no thicker than 10 Angstroms in the current-flow direction, the insulator-material regions individually being directly against one of the pair of source/drain regions.
A memory cell comprising a transistor, the transistor comprising:
- a pair of source/drain regions having a channel there-between;
- a transistor gate construction operatively proximate the channel;
- the channel comprising Si1-yGey, where “y” is from 0 to 0.6;
- and
- at least a portion of each of the source/drain regions comprising Si1-xGex, where “x” is from 0.5 to 1, neither of the portions nor the Si1-xGex therein is directly against the channel, each of the source/drain regions comprises the Si1-yGey and which is directly against the Si1-yGey of the channel, “y” being greater than 0.
A memory cell comprising a transistor, the transistor comprising:
- a pair of solid source/drain regions having a channel there-between;
- a transistor gate construction operatively proximate the channel;
- the channel comprising a direction of current flow there-through between the pair of solid source/drain regions;
- and
- a pair of insulator-material regions in the channel that are each elongated orthogonal to the current-flow direction, are each extending completely through the channel orthogonal to the current-flow direction, and are each no thicker than 10 Angstroms in the current-flow direction, the insulator-material regions individually being directly against one of the pair of source/drain regions.
Dependencies are inferred from the claim text.