Semiconductor layer structure
AssigneeEpinovatech AB
InventorMartin Andreas Olsson
Life of this patent
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AssigneeEpinovatech AB
InventorMartin Andreas Olsson
Estimating the term…
There is provided a semiconductor layer structure (100) comprising: a Si substrate (102) having a top surface (104); a first semiconductor layer (110) arranged on said substrate, the first semiconductor layer comprising a plurality of vertical nanowire structures (112) arranged perpendicularly to said top surface of said substrate, the first semiconductor layer comprising AlN; a second semiconductor layer (120) arranged on said first semiconductor layer laterally and vertically enclosing said nanowire structures, the second semiconductor layer comprising AlxGa1-xN, wherein 0≤x≤0.95; a third semiconductor layer (130) arranged on said second semiconductor layer, the third semiconductor layer comprising AlyGa1-yN, wherein 0≤y≤0.95; and a fourth semiconductor layer (140) arranged on said third semiconductor layer, the fourth semiconductor layer comprising GaN. There is also provided a high-electron-mobility transistor device and methods of producing such structures and devices.
A semiconductor layer structure comprising:
A method for producing a semiconductor layer structure, the method comprising:
Dependencies are inferred from the claim text.