Method of expanding 3D device architectural designs for enhanced performance
AssigneeTokyo Electron Limited
InventorsMark I. Gardner, H. Jim Fulford
Life of this patent
Estimating the term…
Abstract
Aspects of the present disclosure provide a vertical channel 3D semiconductor device sand a method for fabricating the same. The 3D semiconductor devices may have vertical channels of the same or different epitaxially grown doped materials. Sidewall structures are formed around each vertical channel by masking and etching material between the vertical channels. A dielectric layer in each of the sidewalls is etched down to the vertical channel and a gate electrode structure is formed in the opening. The gate electrode structure may include an interfacial oxide, a high-K layer and alternating metal layers. Local interconnects connect to the metal of the gate structure.
Claims20
A method of microfabrication, comprising:
- forming a stack of dielectric layers on a first layer of semiconductor material, the stack of dielectric layers having at least three layers in which a first dielectric material is positioned below and above a second dielectric material, the first dielectric material being different from the second dielectric material in that the second dielectric material can be removed without removing the first dielectric material;
- forming openings in the stack of dielectric layers such that the first layer of semiconductor material is uncovered;
- epitaxially growing channel material within uncovered openings to form vertical channels;
- removing a portion of the stack of dielectric layers such that sidewall structures remain on the vertical channels;
- removing the second dielectric material from the sidewall structures such that sidewall surfaces of the vertical channels are uncovered;
- and
- forming a gate structure on uncovered sidewall surfaces of the vertical channels.
A semiconductor device, comprising:
- a substrate layer;
- a layer of a first dielectric material;
- a layer of semiconductor material;
- a stack of dielectric layers having at least three layers in which the first dielectric material is positioned below and above a second dielectric material, the first dielectric material being different from the second dielectric material in that the second dielectric material can be removed without removing the first dielectric material;
- first openings in the stack of dielectric layers in which the layer of semiconductor material is uncovered;
- vertical channels having epitaxially grown doped material in the first openings;
- sidewall structures formed by second openings in the stack of dielectric layers between the vertical channels;
- third openings in the sidewall structures formed by removal of the second dielectric material to the vertical channel;
- gate structures in the third openings;
- and
- local interconnects connected to the gate structure of each vertical channel, the vertical channels configured to conduct current perpendicular to a working surface of the substrate.
Dependencies are inferred from the claim text.