Passivation layers for semiconductor devices

A semiconductor device, comprising:

• a substrate;
• and
• a gate-all-around (GAA) transistor, comprising:
• a source/drain (S/D) region disposed on the substrate, wherein the S/D region comprises a stack of first and second semiconductor layers arranged in an alternating configuration and an epitaxial region disposed on the stack of first and second semiconductor layers;
• nanostructured channel regions disposed adjacent to the S/D region;
• a passivation layer, wherein a first portion of the passivation layer is disposed between the epitaxial region and the stack of first and second semiconductor layers and a second portion of the passivation layer is disposed on sidewalls of the nanostructured channel regions;
• and
• a nanosheet (NS) structure surrounding the nanostructured channel regions.

A semiconductor device, comprising:

• a substrate;
• first and second fin structures disposed on the substrate;
• a stack of first and second semiconductor layers disposed on each first portion of the first and second fin structures;
• a stack of third semiconductor layers disposed on a second portion of the first fin structure;
• a stack of the fourth semiconductor layers disposed on a second portion of the second fin structure, wherein the third and fourth semiconductor layers have conductivity types different from each other;
• first and second gate structures surrounding the third and fourth semiconductor layers, respectively;
• and
• a passivation layer disposed on the first and second fin structures and along sidewalls of the third and fourth semiconductor layers.