Method of manufacturing a semiconductor device

A method of manufacturing a semiconductor device, the method comprising:

• forming an active pattern on a substrate, the active pattern extending in a first direction substantially parallel to an upper surface of the substrate;
• forming sacrificial lines and semiconductor lines on the active pattern, each of the sacrificial lines and the semiconductor lines extending in the first direction, and the sacrificial lines and the semiconductor lines alternately and repeatedly stacked;
• etching the sacrificial lines and the semiconductor lines to form sacrificial patterns and preliminary semiconductor patterns, respectively, an upper portion of the active pattern being etched to form a first recess;
• partially etching opposite lateral portions in the first direction of each of the sacrificial patterns to form second recesses, respectively;
• performing a first SEG process using surfaces of the preliminary semiconductor patterns and sidewalls of the sacrificial patterns exposed by the second recesses and a surface of the active pattern exposed by the first recess as a seed such that a width in the first direction of each of the preliminary semiconductor patterns is increased to form semiconductor patterns and that a channel connection portion is formed to connect the semiconductor patterns with each other and a lowermost one of the semiconductor patterns and the active pattern with each other;
• forming inner spacers in the second recesses, respectively;
• forming source/drain layers to contact opposite sidewalls in the first direction of the semiconductor patterns, respectively;
• and
• replacing the sacrificial patterns with a gate structure.

A method of manufacturing a semiconductor device, the method comprising:

• alternately and repeatedly stacking sacrificial layers and semiconductor layers on a substrate;
• partially etching the semiconductor layers, the sacrificial layers, and an upper portion of the substrate to form semiconductor lines, sacrificial lines, and an active pattern, respectively, each of the semiconductor lines, the sacrificial lines, and the active pattern extending in a first direction substantially parallel to an upper surface of the substrate;
• forming a dummy gate structure on the active pattern, the dummy gate structure extending in a second direction substantially parallel to the upper surface of the substrate and crossing the first direction;
• forming gate spacers on opposite sidewalls in the first direction of the dummy gate structure, respectively;
• etching the sacrificial lines, the semiconductor lines, and an upper portion of the active pattern to form sacrificial patterns, preliminary semiconductor patterns, and a first recess, respectively;
• partially etching opposite lateral portions in the first direction of each of the sacrificial patterns to form second recesses, respectively;
• performing a first SEG process using surfaces of the preliminary semiconductor patterns and sidewalls of the sacrificial patterns exposed by the second recesses and a surface of the active pattern exposed by the first recess as a seed such that a width in the first direction of each of the preliminary semiconductor patterns is increased to form semiconductor patterns and that a channel connection portion is formed to connect the semiconductor patterns with each other and a lowermost one of the semiconductor patterns and the active pattern with each other;
• forming inner spacers in the second recesses, respectively;
• performing a second SEG using a surface of the active pattern and sidewalls in the first direction of the semiconductor patterns as a seed to form source/drain layers to contact opposite sidewalls in the first direction of the semiconductor patterns, respectively;
• and
• replacing the sacrificial patterns and the dummy gate structure with a gate structure.