Active matrix substrate and method for manufacturing same

An active matrix substrate including a plurality of pixel areas, the active matrix substrate comprising:

• a substrate;
• a plurality of source bus lines supported on a main surface of the substrate and extending in a first direction;
• a lower insulating layer covering the plurality of source bus lines;
• a plurality of gate bus lines formed above the lower insulating layer and extending in a second direction intersecting the first direction;
• and
• an oxide semiconductor TFT and a pixel electrode disposed to correspond to each of the plurality of pixel areas,
• wherein in each of the plurality of pixel areas,
• the oxide semiconductor TFT includes
• an oxide semiconductor layer disposed on the lower insulating layer, the oxide semiconductor layer including a channel region, a first region, and a second region, the first region and the second region being located on respective both sides of the channel region, the first region being electrically connected to a corresponding one of the plurality of source bus lines, the second region being electrically connected to the pixel electrode, and
• a gate electrode disposed on at least the channel region of the oxide semiconductor layer with a gate insulating layer being interposed between the gate electrode and the channel region, the gate electrode being formed in a different layer from the plurality of gate bus lines and being disposed to be separated from another gate electrode disposed in an adjacent one of the plurality of pixel areas,
• the oxide semiconductor layer and the gate electrode are covered by an interlayer insulating layer, and the interlayer insulating layer includes at least one gate contact hole for exposing a part of the gate electrode,
• one of the plurality of gate bus lines is disposed on the interlayer insulating layer and in the at least one gate contact hole, and is electrically connected to the gate electrode in the at least one gate contact hole
• in each of the plurality of pixel areas, when viewed from a normal direction of the main surface of the substrate, the gate electrode of the oxide semiconductor TFT includes a first part overlapping the oxide semiconductor layer and an extending part extending from the first part not to overlap the oxide semiconductor layer, and
• the at least one gate contact hole is disposed to expose a part of the extending part of the gate electrode
• in each of the plurality of pixel areas, the at least one gate contact hole includes a plurality of gate contact holes disposed to be spaced apart from each other
• wherein in each of the plurality of pixel areas, when viewed from the normal direction of the main surface of the substrate,
• the extending part of the gate electrode includes a first extending part and a second extending part disposed on respective both sides of the first part, and
• the plurality of gate contact holes include a first gate contact hole disposed to overlap the first extending part and a second gate contact hole disposed to overlap the second extending part.

An active matrix substrate An active matrix substrate including a plurality of pixel areas, the active matrix substrate comprising:

• a substrate;
• a plurality of source bus lines supported on a main surface of the substrate and extending in a first direction;
• a lower insulating layer covering the plurality of source bus lines;
• a plurality of gate bus lines formed above the lower insulating layer and extending in a second direction intersecting the first direction;
• and
• an oxide semiconductor TFT and a pixel electrode disposed to correspond to each of the plurality of pixel areas,
• wherein in each of the plurality of pixel areas,
• the oxide semiconductor TFT includes
• an oxide semiconductor layer disposed on the lower insulating layer, the oxide semiconductor layer including a channel region, a first region, and a second region, the first region and the second region being located on respective both sides of the channel region, the first region being electrically connected to a corresponding one of the plurality of source bus lines, the second region being electrically connected to the pixel electrode, and
• a gate electrode disposed on at least the channel region of the oxide semiconductor layer with a gate insulating layer being interposed between the gate electrode and the channel region, the gate electrode being formed in a different layer from the plurality of gate bus lines and being disposed to be separated from another gate electrode disposed in an adjacent one of the plurality of pixel areas,
• the oxide semiconductor layer and the gate electrode are covered by an interlayer insulating layer, and the interlayer insulating layer includes at least one gate contact hole for exposing a part of the gate electrode,
• one of the plurality of gate bus lines is disposed on the interlayer insulating layer and in the at least one gate contact hole, and is electrically connected to the gate electrode in the at least one gate contact hole,
• in each of the plurality of pixel areas, when viewed from a normal direction of the main surface of the substrate, the gate electrode extends in the second direction to overlap a corresponding one of the plurality of gate bus lines, and
• in each of the plurality of pixel areas, when viewed from the normal direction of the main surface of the substrate, the entire gate electrode overlaps the corresponding one of the plurality of gate bus lines.

An active matrix substrate including a plurality of pixel areas, the active matrix substrate comprising:

• a substrate;
• a plurality of source bus lines supported on a main surface of the substrate and extending in a first direction;
• a lower insulating layer covering the plurality of source bus lines;
• a plurality of gate bus lines formed above the lower insulating layer and extending in a second direction intersecting the first direction;
• and
• an oxide semiconductor TFT and a pixel electrode disposed to correspond to each of the plurality of pixel areas,
• wherein in each of the plurality of pixel areas,
• the oxide semiconductor TFT includes
• an oxide semiconductor layer disposed on the lower insulating layer, the oxide semiconductor layer including a channel region, a first region, and a second region, the first region and the second region being located on respective both sides of the channel region, the first region being electrically connected to a corresponding one of the plurality of source bus lines, the second region being electrically connected to the pixel electrode, and
• a gate electrode disposed on at least the channel region of the oxide semiconductor layer with a gate insulating layer being interposed between the gate electrode and the channel region, the gate electrode being formed in a different layer from the plurality of gate bus lines and being disposed to be separated from another gate electrode disposed in an adjacent one of the plurality of pixel areas,
• the oxide semiconductor layer and the gate electrode are covered by an interlayer insulating layer, and the interlayer insulating layer includes at least one gate contact hole for exposing a part of the gate electrode,
• one of the plurality of gate bus lines is disposed on the interlayer insulating layer and in the at least one gate contact hole, and is electrically connected to the gate electrode in the at least one gate contact hole,
• in each of the plurality of pixel areas, when viewed from a normal direction of the main surface of the substrate, the gate electrode of the oxide semiconductor TFT includes a first part overlapping the oxide semiconductor layer and an extending part extending from the first part not to overlap the oxide semiconductor layer,
• the at least one gate contact hole is disposed to expose a part of the extending part of the gate electrode,
• in each of the plurality of pixel areas, the oxide semiconductor layer further includes another channel region,
• when viewed from a normal direction of the main surface of the substrate, the gate electrode further includes a second part overlapping the another channel region, the extending part of the gate electrode includes a third part being located between the first part and the second part, and
• the at least one gate contact hole is disposed on the third part of the extending part.

An active matrix substrate including a plurality of pixel areas, the active matrix substrate comprising:

• a substrate;
• a plurality of source bus lines supported on a main surface of the substrate and extending in a first direction;
• a lower insulating layer covering the plurality of source bus lines;
• a plurality of gate bus lines formed above the lower insulating layer and extending in a second direction intersecting the first direction;
• and
• an oxide semiconductor TFT and a pixel electrode disposed to correspond to each of the plurality of pixel areas, wherein
• the oxide semiconductor TFT includes
• an oxide semiconductor layer disposed on the lower insulating layer, the oxide semiconductor layer including a channel region, a first region, and a second region, the first region and the second region being located on respective both sides of the channel region, the first region being electrically connected to a corresponding one of the plurality of source bus lines, and
• a gate electrode disposed on at least the channel region of the oxide semiconductor layer with a gate insulating layer being interposed between the gate electrode and the channel region,
• the oxide semiconductor layer and the gate electrode are covered by an interlayer insulating layer,
• the oxide semiconductor TFT further includes
• a source electrode integrally formed by using a same conductive film as the corresponding one of the plurality of source bus lines,
• a connection electrode being formed in a same layer as the gate electrode, and
• a first insulating layer being disposed between the connection electrode and the lower insulating layer and being formed in a same layer as the gate insulating layer,
• the lower insulating layer includes a source opening for exposing a part of the source electrode,
• the first insulating layer includes a first opening for exposing a part of the first region of
• the oxide semiconductor layer, and at least partially overlapping the source opening when viewed from a normal direction of the main surface of the substrate, and
• the connection electrode is electrically connected to the part of the first region of the oxide semiconductor layer and the part of the source electrode in a source contact hole including the source opening of the lower insulating layer and the first opening of the first insulating layer, and contacts with an edge of the first region.

A manufacturing method of an active matrix substrate including a plurality of pixel areas and an oxide semiconductor TFT disposed to correspond to each of the plurality of pixel areas, the manufacturing method comprising the steps of:

• (a) forming a source conductive film on a substrate and performing patterning of the source conductive film to thereby form a source metal layer including a plurality of source bus lines and a source electrode of the oxide semiconductor TFT in each of the plurality of pixel areas, the source electrode in each of the plurality of pixel areas being electrically connected to one corresponding source bus line out of the plurality of source bus lines;
• (b) forming a lower insulating layer on the source metal layer, and in each of the plurality of pixel areas, forming a source opening for exposing a part of the source electrode of the oxide semiconductor TFT in the lower insulating layer;
• (c) in each of the plurality of pixel areas, forming an oxide semiconductor layer of the oxide semiconductor TFT on the lower insulating layer and in the source opening, the oxide semiconductor layer being electrically connected to the source electrode in the source opening;
• (d) in each of the plurality of pixel areas, forming a gate electrode on a part of the oxide semiconductor layer with a gate insulating layer being interposed between the gate electrode and the part of the oxide semiconductor layer;
• (e) in each of the plurality of pixel areas, forming an interlayer insulating layer to cover the oxide semiconductor layer and the gate electrode, and forming at least one gate contact hole for exposing a part of the gate electrode in the interlayer insulating layer;
• (f) forming a gate conductive film on the interlayer insulating layer and performing patterning of the gate conductive film to thereby form a gate metal layer including the plurality of gate bus lines, one gate bus line out of the plurality of gate bus lines being electrically connected to the gate electrode in the at least one gate contact hole in each of the plurality of pixel areas;
• and
• (g) forming a pixel electrode in each of the plurality of pixel areas, the pixel electrode being electrically connected to the oxide semiconductor layer of the oxide semiconductor TFT.

A manufacturing method of an active matrix substrate including a plurality of pixel areas and an oxide semiconductor TFT disposed to correspond to each of the plurality of pixel areas, the manufacturing method comprising the steps of:

• (A) forming a source conductive film on a substrate and performing patterning of the source conductive film to thereby form a source metal layer including a plurality of source bus lines and a source electrode of the oxide semiconductor TFT in each of the plurality of pixel areas, the source electrode in each of the plurality of pixel areas being electrically connected to one corresponding source bus line out of the plurality of source bus lines;
• (B) forming a lower insulating layer on the source metal layer;
• (C) in each of the plurality of pixel areas, forming an oxide semiconductor layer of the oxide semiconductor TFT on the lower insulating layer;
• (D) in each of the plurality of pixel areas, forming a gate insulating film to cover the oxide semiconductor layer, and forming a source contact hole for exposing a part of the source electrode and a part of the oxide semiconductor layer in the gate insulating film and the lower insulating layer;
• (E) forming a gate electrode film on the gate insulating film and performing patterning of the gate electrode film and the gate insulating film to thereby form a gate insulating layer and a first insulating layer out of the gate insulating film, and forming a gate electrode located on the gate insulating layer and a connection electrode located on the first insulating layer out of the gate electrode film, the connection electrode being electrically connected to the part of the oxide semiconductor layer and the part of the source electrode in the source contact hole;
• (F) in each of the plurality of pixel areas, forming an interlayer insulating layer to cover the oxide semiconductor layer, the connection electrode, and the gate electrode, and forming at least one gate contact hole for exposing a part of the gate electrode in the interlayer insulating layer;
• (G) forming a gate conductive film on the interlayer insulating layer and performing patterning of the gate conductive film to thereby form a gate metal layer including the plurality of gate bus lines, one gate bus line out of the plurality of gate bus lines being electrically connected to the gate electrode in the at least one gate contact hole in each of the plurality of pixel areas;
• and
• (H) forming a pixel electrode in each of the plurality of pixel areas, the pixel electrode being electrically connected to the oxide semiconductor layer of the oxide semiconductor TFT.