Integrated circuit layout cell, integrated circuit layout arrangement, and methods of forming the same

An integrated circuit layout arrangement comprising:

• a first integrated circuit layout cell comprising:
• a doped region of a first conductivity type;
• a doped region of a second conductivity type opposite of the first conductivity type;
• a further doped region of the first conductivity type at least partially within the doped region of the second conductivity type, and continuous with the doped region of the first conductivity type;
• a first transistor having a control terminal, a first controlled terminal, and a second controlled terminal, the first controlled terminal and the second controlled terminal of the first transistor comprising terminal regions of the second conductivity type formed within the further doped region of the first conductivity type;
• a second transistor having a control terminal, a first controlled terminal, and a second controlled terminal, the first controlled terminal and the second controlled terminal of the second transistor comprising terminal regions of the first conductivity type;
• wherein the first controlled terminal of the first transistor is in electrical connection with the first controlled terminal of the second transistor;
• and
• wherein the second controlled terminal of the first transistor is in electrical connection with the second controlled terminal of the second transistor;
• and
• a second integrated circuit layout cell comprising a p-channel transistor and an n-channel transistor;
• wherein the p-channel transistor of the second integrated circuit layout cell comprises a control terminal, a first controlled terminal, and a second controlled terminal;
• wherein the n-channel transistor of the second integrated circuit layout cell comprises a control terminal, a first controlled terminal, and a second controlled terminal;
• wherein the first controlled terminal of the p-channel transistor of the second integrated circuit layout cell is in electrical connection with the first controlled terminal of the n-channel transistor of the second integrated circuit layout cell;
• and
• wherein the second controlled terminal of the p-channel transistor of the second integrated circuit layout cell is in electrical connection with the second controlled terminal of the n-channel transistor of the second integrated circuit layout cell.

A method of forming an integrated circuit layout cell, the method comprising:

• forming a doped region of a first conductivity type;
• forming a doped region of a second conductivity type opposite of the first conductivity type;
• forming a further doped region of the first conductivity type at least partially within the doped region of the second conductivity type, and continuous with the doped region of the first conductivity type;
• forming a first transistor having a control terminal, a first controlled terminal, and a second controlled terminal, the first controlled terminal and the second controlled terminal of the first transistor comprising terminal regions of the second conductivity type formed within the further doped region of the first conductivity type;
• forming a second transistor having a control terminal, a first controlled terminal, and a second controlled terminal, the first controlled terminal and the second controlled terminal of the second transistor comprising terminal regions of the first conductivity type;
• wherein the first controlled terminal of the first transistor is in electrical connection with the first controlled terminal of the second transistor;
• and
• wherein the second controlled terminal of the first transistor is in electrical connection with the second controlled terminal of the second transistor.

A method of forming an integrated circuit layout arrangement, the method comprising:

• forming a first integrated circuit layout cell comprising:
• a doped region of a first conductivity type;
• a doped region of a second conductivity type opposite of the first conductivity type;
• a further doped region of the first conductivity type at least partially within the doped region of the second conductivity type, and continuous with the doped region of the first conductivity type;
• a first transistor having a control terminal, a first controlled terminal, and a second controlled terminal, the first controlled terminal and the second controlled terminal of the first transistor comprising terminal regions of the second conductivity type formed within the further doped region of the first conductivity type;
• a second transistor having a control terminal, a first controlled terminal, and a second controlled terminal, the first controlled terminal and the second controlled terminal of the second transistor comprising terminal regions of the first conductivity type;
• wherein the first controlled terminal of the first transistor is in electrical connection with the first controlled terminal of the second transistor;
• and
• wherein the second controlled terminal of the first transistor is in electrical connection with the second controlled terminal of the second transistor;
• and
• forming a second integrated circuit layout cell comprising a p-channel transistor and an n-channel transistor;
• wherein the p-channel transistor of the second integrated circuit layout cell comprises a control terminal, a first controlled terminal, and a second controlled terminal;
• wherein the n-channel transistor of the second integrated circuit layout cell comprises a control terminal, a first controlled terminal, and a second controlled terminal;
• wherein the first controlled terminal of the p-channel transistor of the second integrated circuit layout cell is in electrical connection with the first controlled terminal of the n-channel transistor of the second integrated circuit layout cell;
• and
• wherein the second controlled terminal of the p-channel transistor of the second integrated circuit layout cell is in electrical connection with the second controlled terminal of the n-channel transistor of the second integrated circuit layout cell.