US 11,695,007 B2 · Guard ring capacitor method and structure

Abstract

A method of biasing a guard ring structure includes biasing a gate of a MOS transistor to a first bias voltage level, biasing first and second S/D regions of the MOS transistor to a power domain voltage level, biasing a gate of the guard ring structure to a second bias voltage level, and biasing first and second heavily doped regions of the guard ring structure to the power domain voltage level. Each of the first and second S/D regions has a first doping type, each of the first and second heavily doped regions has a second doping type different from the first doping type, and each of the first and second S/D regions and the first and second heavily doped regions is positioned in a substrate region having the second doping type.

Claims20

Dependent claims

An integrated circuit (IC) device comprising:

a metal oxide semiconductor (MOS) transistor comprising:
first and second source/drain (S/D) regions, each of the first and second S/D regions having a first doping type;
and
a first gate electrode overlying a substrate region having a second doping type different from the first doping type;
and
a guard ring structure surrounding the MOS transistor, the guard ring structure comprising:
first and second heavily doped regions, each of the first and second heavily doped regions having the second doping type;
and
a second gate electrode overlying the substrate region between the first and second heavily doped regions,
wherein each of the first gate electrode and the second gate electrode is configured to receive a same bias voltage level.

7 more elements

An integrated circuit (IC) device comprising:

a metal oxide semiconductor (MOS) transistor comprising:
first and second source/drain (S/D) regions, each of the first and second S/D regions having a first doping type;
and
a transistor gate electrode overlying a substrate region having a second doping type different from the first doping type;
and
a guard ring structure surrounding the MOS transistor, the guard ring structure comprising:
first and second heavily doped regions, each of the first and second heavily doped regions having the second doping type;
and
a guard ring gate electrode overlying the substrate region between the first and second heavily doped regions,
wherein
each of the transistor gate electrode and the guard ring gate electrode is configured to receive a same bias voltage level, and
each of the first and second S/D regions and each of the first and second heavily doped regions is configured to receive a same power domain voltage level.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/030,122Filed 23 Sep 2020 · us provisional application

Priority

31 Mar 2020

Published

US 2021/0305248 A130 Sep 2021

Granted

4 Jul 2023

Term ends

Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 1/66
Capacitors having potential barriers: conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
H10D 84/854
Complementary IGFETs, e.g. CMOS: comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for…
H03K 17/6872
The output circuit comprising more than one controlled field-effect transistor: using complementary field-effect transistors
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions

Guard ring capacitor method and structure

Life of this patent

Guard ring capacitor method and structure

Life of this patent

Abstract

Claims20