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US 11,695,005 B2Granted
Fabricating gate-all-around transistors having high aspect ratio channels and reduced parasitic capacitance
AssigneeInternational Business Machines Corporation
InventorEffendi Leobandung
Life of this patent
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Abstract
Embodiments of the invention are directed to a semiconductor-based structure. A non-limiting example of the semiconductor-based structure includes a fin formed over a substrate. A tunnel is formed through the fin to define an upper fin region and a lower fin region. A gate structure is configured to wrap around a circumference of the upper fin region.
Claims20
A semiconductor-based structure comprising:
- a fin formed over a substrate;
- a fin tunnel formed through the fin to define an upper fin region and a lower fin region spaced-apart from the upper fin region;
- and
- a gate structure configured to wrap around a circumference of the upper fin region.
1 more element
A semiconductor-based structure comprising:
- a first fin and a second fin formed over a substrate;
- a first fin tunnel formed through the first fin to define an upper first fin region and a lower first fin region spaced-apart from the upper first fin region;
- a second fin tunnel formed through the second fin to define an upper second fin region and a lower second fin region spaced-apart from the upper second fin region;
- and
- a gate structure configured to wrap around:
- a circumference of the upper first fin region;
- and
- a circumference of the upper second fin region.
5 more elements
Dependencies are inferred from the claim text.