Integrated circuit including integrated standard cell structure

An integrated circuit comprising:

• a first standard cell including a first p-type transistor and a first n-type transistor;
• a second standard cell which includes a second p-type transistor and second n-type transistor and is disposed to be adjacent to the first standard cell in a first direction;
• a filler cell which includes a first dummy gate stack and a second dummy gate stack disposed between the first standard cell and the second standard cell, the first dummy gate stack and the second dummy gate stack extending in a second direction different from the first direction;
• and
• a power rail extending in the first direction and connected to the first dummy gate stack and the second dummy gate stack,
• wherein:
• the filler cell has a one-pitch dimension,
• the first dummy gate stack and the second dummy gate stack are spaced the one-pitch dimension apart from each other in the first direction,
• the first dummy gate stack of the filler cell is disposed at a boundary between the first standard cell and the filler cell,
• the second dummy gate stack of the filler cell is disposed at a boundary between the second standard cell and the filler cell,
• the first standard cell includes a first gate stack extending in the second direction,
• the second standard cell includes a second gate stack extending in the second direction, and
• a length of each of the first dummy gate stack and the second dummy gate stack is greater than a length of each of the first gate stack and the second gate stack.

An integrated circuit comprising:

• a first standard cell including a first p-type transistor and a first n-type transistor;
• a second standard cell which includes a second p-type transistor and a second n-type transistor and is spaced apart from the first standard cell in a first direction;
• a filler cell which includes a first dummy gate stack and a second dummy gate stack disposed between the first standard cell and the second standard cell, a first filler contact connected to the first dummy gate stack, and a second filler contact connected to the second dummy gate stack, the first dummy gate stack and the second dummy gate stack extending in a second direction different from the first direction;
• and
• a power rail extending in the first direction and connected to the first dummy gate stack via the first filler contact and the second dummy gate stack via the second filler contact,
• wherein:
• the filler cell has a one-pitch dimension,
• the first dummy gate stack and the second dummy gate stack are spaced the one-pitch dimension apart from each other in the first direction,
• the first dummy gate stack of the filler cell is disposed at a boundary between the first standard cell and the filler cell,
• the second dummy gate stack of the filler cell is disposed at a boundary between the second standard cell and the filler cell,
• the first p-type transistor and the second p-type transistor are formed on a first active region,
• the first n-type transistor and the second n-type transistor are formed on a second active region,
• the filler cell further includes a dummy gate cutting pattern on an active region separation film extending in the first direction across a space between the first active region and the second active region,
• the first dummy gate stack includes a first portion and a second portion separated by the dummy gate cutting pattern,
• the second dummy gate stack includes a first portion and a second portion separated by the dummy gate cutting pattern,
• the first filler contact includes a first upper filler contact connected to the first portion of the first dummy gate stack, and a first lower filler contact connected to the second portion of the first dummy gate stack,
• the second filler contact includes a second upper filler contact connected to the first portion of the second dummy gate stack, and a second lower filler contact connected to the second portion of the second dummy gate stack, and
• the first upper filler contact, the first lower filler contact, the second upper filler contact, and the second lower filler contact overlap a cell separation film extending in the first direction along a boundary of the first standard cell, a boundary of the filler cell, and a boundary of the second standard cell.