Discrete three-dimensional processor

A discrete three-dimensional (3-D) processor, comprising:

• said 3D-M array stores at least a portion of a look-up table (LUT) of a non-arithmetic function/model;
• said logic circuit comprises an arithmetic logic circuit (ALC) for performing arithmetic operations on selected data from said LUT;
• whereby said 3-D processor computes said non-arithmetic function/model, wherein said non-arithmetic function/model includes more operations than the arithmetic operations provided by said ALC;
• or,
• said 3D-M array is a portion of a configurable computing element (CCE) and stores at least a portion of a look-up table (LUT) of a non-arithmetic function;
• said logic circuit comprises at least a configurable logic element (CLE) and/or a configurable interconnect (CIT);
• whereby said 3-D processor customizes said non-arithmetic function by programming said CCE and said CLE/CIT, wherein said non-arithmetic function includes more operations than the arithmetic operations provided by said CLE;
• or,
• said 3-D processor further comprises an input for transferring at least a first portion of a first pattern;
• said 3D-M array stores at least a second portion of a second pattern;
• said logic circuit comprises a pattern-processing circuit for performing pattern processing for said first and second patterns;
• or,
• said 3-D processor is a discrete 3-D processor with embedded search-pattern library, further comprising an input for transferring at least a target pattern;
• said 3D-M array stores at least a search pattern;
• said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern;
• or,
• said 3-D processor is a discrete 3-D storage with in-situ pattern-processing capabilities, further comprising an input for transferring at least a search pattern;
• said 3D-M array stores at least a target pattern;
• said logic circuit comprises a pattern-processing circuit for searching said target pattern for said search pattern;
• or,
• a first die on a first semiconductor substrate, comprising at least a 3D-M array including a plurality of memory cells stacked above said first semiconductor substrate;
• a second die on a second semiconductor substrate, comprising at least a logic circuit and at least a portion of a sense amplifier of said 3D-M array disposed on said second semiconductor substrate;
• wherein, said logic circuit processes data stored in said 3D-M array;
• said logic circuit is not a portion of a peripheral circuit of said 3D-M array;
• said first die does not comprise said portion of said sense amplifier;
• said first and second dice are communicatively coupled by a plurality of inter-die connections;
• said first and second semiconductor substrates are separate substrates.

A discrete three-dimensional (3-D) processor, comprising:

• a first die on a first semiconductor substrate, comprising at least a 3D-M array including a plurality of memory cells stacked above said first semiconductor substrate;
• a second die on a second semiconductor substrate, comprising at least a logic circuit and at least a portion of a programming circuit of said 3D-M array disposed on said second semiconductor substrate;
• wherein, said logic circuit processes data stored in said 3D-M array;
• said logic circuit is not a portion of a peripheral circuit of said 3D-M array;
• said first die does not comprise said portion of said programming circuit;
• said first and second dice are communicatively coupled by a plurality of inter-die connections;
• said first and second semiconductor substrates are separate substrates.

A discrete three-dimensional (3-D) processor, comprising:

• a first die on a first semiconductor substrate, comprising at least a 3D-M array including a plurality of memory cells stacked above said first semiconductor substrate;
• a second die on a second semiconductor substrate, comprising at least a logic circuit and at least a portion of a read-voltage generator of said 3D-M array disposed on said second semiconductor substrate;
• wherein, said logic circuit processes data stored in said 3D-M array;
• said logic circuit is not a portion of a peripheral circuit of said 3D-M array;
• said first die does not comprise said portion of said read-voltage generator;
• said first and second dice are communicatively coupled by a plurality of inter-die connections;
• said first and second semiconductor substrates are separate substrates.

A discrete three-dimensional (3-D) processor, comprising:

• a first die on a first semiconductor substrate, comprising at least a 3D-M array including a plurality of memory cells stacked above said first semiconductor substrate;
• a second die on a second semiconductor substrate, comprising at least a logic circuit and at least a portion of a write-voltage generator of said 3D-M array disposed on said second semiconductor substrate;
• wherein, said logic circuit processes data stored in said 3D-M array;
• said logic circuit is not a portion of a peripheral circuit of said 3D-M array;
• said first die does not comprise said portion of said write-voltage generator;
• said first and second dice are communicatively coupled by a plurality of inter-die connections;
• said first and second semiconductor substrates are separate substrates.

A discrete three-dimensional (3-D) processor, comprising:

• a first die on a first semiconductor substrate, comprising at least a 3D-M array including a plurality of memory cells stacked above said first semiconductor substrate;
• a second die on a second semiconductor substrate, comprising at least a logic circuit and at least a portion of a data buffer of said 3D-M array disposed on said second semiconductor substrate;
• wherein, said logic circuit processes data stored in said 3D-M array;
• said logic circuit is not a portion of a peripheral circuit of said 3D-M array;
• said first die does not comprise said portion of said data buffer;
• said first and second dice are communicatively coupled by a plurality of inter-die connections;
• said first and second semiconductor substrates are separate substrates.