Semiconductor package including a pad contacting a via

A semiconductor package, comprising:

• a first sub-semiconductor package and a second sub-semiconductor package, which are sequentially stacked, wherein:
• the first sub-semiconductor package comprises a first redistribution structure, a first semiconductor die connected to the first redistribution structure, a first mold layer covering a side surface of the first semiconductor die and a top surface of the first redistribution structure, and a first mold via penetrating the first mold layer,
• the second sub-semiconductor package comprises a second redistribution structure, a second semiconductor die connected to the second redistribution structure, and a second mold layer covering a side surface of the second semiconductor die and a top surface of the second redistribution structure,
• the second redistribution structure comprises a first redistribution pad contacting the first mold via,
• the first semiconductor die comprises a first through-substrate via, and
• the second redistribution structure further comprises a second redistribution pad contacting the first through-substrate via.

A semiconductor package, comprising:

• a first semiconductor die;
• a plurality of second semiconductor dies stacked on the first semiconductor die, each of the second semiconductor dies having a width smaller than a width of the first semiconductor die;
• and
• a mold layer covering side surfaces of the second semiconductor dies and a top surface of the first semiconductor die,
• wherein the first semiconductor die comprises a first substrate, a first interlayer insulating layer disposed on a front surface of the first substrate, a first interconnection line disposed in the first interlayer insulating layer, a first protection layer covering a rear surface of the first substrate, and a first through via penetrating the first protection layer and the first substrate,
• each of the second semiconductor dies comprises a second substrate, a second interlayer insulating layer disposed on a front surface of the second substrate, a second passivation layer covering the second interlayer insulating layer, a second conductive pad disposed in the second passivation layer, a second interconnection line disposed in the second interlayer insulating layer, a second protection layer covering a rear surface of the second substrate, and a second through via penetrating the second protection layer and the second substrate,
• the first through via contacts the second conductive pad of a lowermost one of the second semiconductor dies, and
• the second through via of the lowermost one of the second semiconductor dies has an aspect ratio equal to or greater than 5.