A semiconductor chip stack structure comprising a first semiconductor chip and a second semiconductor chip on the first semiconductor chip:
- the first semiconductor chip comprising:
- a first semiconductor substrate having an active surface and a non-active surface opposite to the active surface;
- a first semiconductor device layer formed on the active surface and including a circuit pattern;
- a first rear surface insulating layer formed on the non-active surface;
- a plurality of first rear surface pads formed at a same level as the first rear surface insulating layer;
- a first front surface insulating layer formed on the first semiconductor device layer and spaced apart from the first semiconductor substrate with the first semiconductor device layer interposed therebetween;
- a plurality of first front surface pads formed at a same level as the first front surface insulating layer;
- a plurality of first through electrodes configured to pass through the first semiconductor substrate and the first semiconductor device layer and to be electrically connected to the plurality of first rear surface pads, respectively, and the plurality of first front surface pads, respectively;
- a first polymer layer formed on the first front surface insulating layer;
- a plurality of first under bump metallurgy (UBM) patterns buried in the first polymer layer;
- and
- a plurality of first buried solders formed on the plurality of first UBM patterns, respectively, and buried in the first polymer layer;
- and
- the second semiconductor chip comprising:
- a second semiconductor substrate having an active surface and a non-active surface opposite to the active surface;
- a second semiconductor device layer formed on the active surface of the second semiconductor substrate and including a circuit pattern;
- a second front surface insulating layer formed on the second semiconductor device layer and spaced apart from the second semiconductor substrate with the second semiconductor device layer interposed therebetween;
- a plurality of second front surface pads formed at a same level as the second front surface insulating layer;
- a second polymer layer formed on the second front surface insulating layer;
- a plurality of second UBM patterns buried in the second polymer layer;
- and
- a plurality of second buried solders formed on the plurality of second UBM patterns, respectively, and buried in the second polymer layer,
- wherein a lower surface of the plurality of second buried solders is coplanar with a lower surface of the second polymer layer, the lower surface of the second polymer layer is in contact with the first rear surface insulating layer,
- wherein the plurality of second buried solders contact the plurality of first rear surface pads, respectively,
- wherein each of the plurality of second buried solders comprises a first portion having a horizontal cross-sectional area that is constant and a second portion having a horizontal cross-sectional area that changes,
- wherein the first portion and the second portion of each of the plurality of second buried solders include a same material, and
- wherein the horizontal cross-sectional area of the second portion of each of the plurality of second buried solders increases as a distance from a contact surface with the first rear surface pad decreases, and the horizontal cross-sectional area of each of the plurality of second buried solders is less than a horizontal cross-sectional area of the first rear surface pad.