Near tier decoupling capacitors

An integrated circuit package structure comprising:

• a chip carrier substrate;
• at least one processor die provided on the chip carrier substrate;
• a plurality of lateral escape wiring lines connected to and extending away from the at least one processor die;
• and
• a plurality of chips at least partially surrounding the processor die, at least one of the chips overlapping with at least one of the lateral escape wiring lines in a plan view without electrically connecting to the at least one of the lateral escape wiring lines,
• wherein an interconnect structure of the at least one of the chips includes at least one vertical power feed structure that is configured and positioned not to overlap with the at least one of the lateral escape wiring lines in the plan view.