Vias in composite IC chip structures

A method for fabricating an IC device structure, the method comprising:

• forming a first metallization layer over first and second regions of a first device layer;
• bonding a chiplet over the first region of the first device layer, the chiplet comprising a second device layer;
• forming one or more conductive vias adjacent to an edge sidewall of the chiplet, wherein forming the one or more conductive vias adjacent to the edge sidewall of the chiplet comprises embedding the chiplet in a fill dielectric, forming a trench in the fill dielectric adjacent the edge sidewall, and filling the trench with a metal;
• and
• forming a top metallization layer over the chiplet and over the second region of the first device layer, wherein the top metallization layer comprises a plurality of first level interconnect (FLI) interfaces.

A method for fabricating an IC device structure, the method comprising:

• forming a first metallization layer over first and second regions of a first device layer;
• bonding a chiplet over the first region of the first device layer, the chiplet comprising a second device layer;
• forming one or more conductive vias adjacent to an edge sidewall of the chiplet, wherein a first conductive via of the one or more conductive vias is on the edge sidewall of the chiplet;
• and
• forming a top metallization layer over the chiplet and over the second region of the first device layer, wherein the top metallization layer comprises a plurality of first level interconnect (FLI) interfaces.