Three dimensional integrated semiconductor architecture having alignment marks provided in a carrier substrate
AssigneeSamsung Electronics Co., Ltd.
InventorsSeok Won Cho, Ki-Il Kim, Kang Ill Seo
Life of this patent
Estimating the term…
Abstract
Provided is a semiconductor architecture including a carrier substrate, alignment marks provided in the carrier substrate, the alignment marks being provided from a first surface of the carrier substrate to a second surface of the carrier substrate, a first semiconductor device provided on the first surface of the carrier substrate based on the alignment marks, a second semiconductor device provided on the second surface of the carrier substrate based on the alignment marks and aligned with the first semiconductor device.
Claims10
A semiconductor architecture comprising:
- a carrier substrate;
- alignment marks provided in the carrier substrate, the alignment marks being provided from a first surface of the carrier substrate to a second surface of the carrier substrate;
- a first semiconductor device provided on the first surface of the carrier substrate based on the alignment marks, the first semiconductor device comprising a buried power rail (BPR) that is extended in a horizontal direction, and formed at an active device level different from metal interconnect structures;
- and
- a second semiconductor device provided on the second surface of the carrier substrate based on the alignment marks and aligned with the first semiconductor device,
- wherein a through-silicon via (TSV) penetrates through the carrier substrate in a vertical direction, perpendicular to the horizontal direction, and contacts the BPR and the second semiconductor device.
A semiconductor architecture comprising:
- a wafer;
- alignment marks provided in the wafer, the alignment marks being openings provided from a first surface of the wafer to a second surface of the wafer that is opposite to the first surface;
- a first semiconductor device provided on the first surface of the wafer based on the alignment marks, the first semiconductor device comprising a buried power rail (BPR) extended in a horizontal direction;
- and
- a second semiconductor device provided on the second surface of the wafer based on the alignment marks and aligned with the first semiconductor device,
- wherein a through-silicon via (TSV) penetrates through the wafer in a vertical direction, perpendicular to the horizontal direction, and contacts the BPR and the second semiconductor device.
Dependencies are inferred from the claim text.