Fan-out semiconductor package

A fan-out semiconductor package comprising:

• a connection structure, having an upper surface, and including a first redistribution layer below the upper surface;
• a semiconductor chip, disposed on the upper surface of the connection structure, and having a front surface on which a connection pad is disposed, a back surface opposite to the front surface, and side surfaces between the front surface and the back surface, the connection pad electrically connected to the first redistribution layer;
• a first encapsulant, surrounding the back surface of the semiconductor chip and the side surfaces of the semiconductor chip, and having a top surface, spaced apart from the back surface of the semiconductor chip, and side surfaces extending from the top surface of the first encapsulant to the upper surface of the connection structure;
• a second encapsulant, surrounding the top surface of the first encapsulant and the side surfaces of the first encapsulant, and having a top surface spaced apart from the top surface of the first encapsulant;
• and
• a second redistribution layer, disposed on the top surface of the second encapsulant, and electrically connected to the first redistribution layer through an electrical connection path penetrating through the second encapsulant.

A fan-out semiconductor package comprising:

• a connection structure, having an upper surface, and including a first redistribution layer below the upper surface;
• a semiconductor chip, disposed on the upper surface of the connection structure, and having a front surface on which a connection pad is disposed, a back surface opposite to the front surface, and side surfaces between the front surface and the back surface, the connection pad electrically connected to the first redistribution layer;
• a first encapsulant, surrounding the side surfaces of the semiconductor chip, and having side surfaces spaced apart from the side surfaces of the semiconductor chip;
• a second encapsulant, surrounding the side surfaces of the first encapsulant, and covering the back surface of the semiconductor chip;
• and
• a conductor structure, extending in a direction perpendicular to the upper surface of the connection structure within the second encapsulant, and electrically connected to the first redistribution layer.