Layout design for threshold voltage tuning
AssigneeInternational Business Machines Corporation
InventorsHuimei Zhou, Su Chen Fan, Miaomiao Wang, Zuoguang Liu
Life of this patent
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Abstract
Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.
Claims13
A semiconductor device, comprising:
- at least one first metal line in contact with a source or drain of a field-effect transistor (FET);
- at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line;
- and
- an oxygen diffusion blocking layer on top of the at least one first metal line in only an overlap area of the at least one first metal line and the at least one second metal line.
A semiconductor device, comprising:
- at least one first FET and at least one second FET;
- at least one first metal line in contact with a source or drain of the at least one first FET;
- at least one second metal line in contact with a gate of the at least one first FET, wherein the first metal line crosses the second metal line;
- an oxygen diffusion blocking layer on top of the at least one first metal line in only an overlap area of the at least one first metal line and the at least one second metal line;
- a first vertical interconnect (V0) present over the at least one first metal line and the oxygen diffusion blocking layer in the overlap area of the at least one first metal line and the at least one second metal line;
- at least one third metal line in contact with a source or drain of the at least one second FET;
- at least one fourth metal line in contact with a gate of the at least one second FET, wherein the third metal line crosses the fourth metal line;
- and
- a second V0 present over the at least one third metal line away from an overlap area of the at least one third metal line and the at least one fourth metal line.
Dependencies are inferred from the claim text.