US 11,694,951 B2Granted

Zero-misalignment two-via structures

AssigneeIntel Corporation

InventorsVeronica Strong, Aleksandar Aleksov, Brandon Rawlings, Johanna Swan

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Abstract

A device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS is directly coupled to the interconnect. The ZM2VS may further include the dielectric on a conductive pad, a first via on a first seed, and the first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS may also have a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

Claims21

Dependent claims

A device package, comprising:

an interposer with an interconnect on an interconnect package layer;
a conductive layer on the interposer;
and
one or more dies on the conductive layer, wherein the interconnect package layer comprises:
a dielectric layer on a conductive pad;
a first via on a first material layer, the first material layer on a top surface of the conductive pad, wherein the first via extends through the dielectric layer, and wherein the first material layer comprises a material selected from the group consisting of copper, a combination of copper and titanium, a combination of copper and tantalum, and a combination of copper and tungsten;
a conductive trace on the dielectric layer;
and
a second via on a second material layer, the second material layer on the dielectric layer, wherein the conductive trace connects to the first via and the second via, wherein the second via connects to an edge of the conductive trace that is opposite from the first via, and wherein the second material layer comprises a material selected from the group consisting of copper, a combination of copper and titanium, a combination of copper and tantalum, and a combination of copper and tungsten.

6 more elements

A method of forming a device package, comprising:

disposing an interposer with an interconnect on an interconnect package layer;
disposing a conductive layer on the interposer;
and
disposing one or more dies on the conductive layer, wherein forming the interconnect package layer comprises:
disposing a dielectric layer on a conductive pad;
disposing a first via on a first material layer, the first material layer on a top surface of the conductive pad, wherein the first via extends through the dielectric layer, and wherein the first material layer comprises a material selected from the group consisting of copper, a combination of copper and titanium, a combination of copper and tantalum, and a combination of copper and tungsten;
disposing a conductive trace on the dielectric layer;
and
disposing a second via on a second material layer, the second material layer is on the dielectric layer, wherein the conductive trace connects to the first via and the second via, wherein the second via connects to an edge of the conductive trace that is opposite from the first via, and wherein the second material layer comprises a material selected from the group consisting of copper, a combination of copper and titanium, a combination of copper and tantalum, and a combination of copper and tungsten.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/537,406Filed 29 Nov 2021 · continuation
Published: US 2022/0084931 A117 Mar 2022
Granted: 4 Jul 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification20 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10W 70/65
Characterised by their interconnections: shapes or dispositions of interconnections
H10W 20/045
The barrier, adhesion or liner layers being seed or nucleation layers: for deposition from the gaseous phase, e.g. for chemical vapour deposition…
H10W 20/20
Interconnections in chips, wafers or substrates: interconnections within wafers or substrates, e.g. through-silicon vias [TSV]

Family

PCT/US2017/069153Parent of this continuation · filed 30 Dec 2017
US 2022/0084931 A1Pre-grant publication · published 17 Mar 2022
Application16/649,578Parent of this continuation
US 11,222,836 B2Parent of this continuation
US 2020/0294901 A1Published application
US 11,694,951 B2This patent

From the US filing history. Foreign family members aren’t listed.