Semiconductor package
AssigneePowertech Technology Inc.
InventorsChih-Yen Su, Chun-Te Lin
Life of this patent
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Abstract
A semiconductor package has a substrate, a chip and an encapsulation. The substrate has a dielectric layer, a copper wiring layer and a solder resist layer formed thereon. The copper wiring layer is formed on the dielectric layer and is covered by the solder resist layer. The solder resist layer has a chip area defined thereon and an annular opening formed thereon. The annular opening surrounds the chip area and exposes part of the copper wiring layer. The chip is mounted on the chip area and is encapsulated by the encapsulation. Therefore, the semiconductor package with the annular opening makes the solder resist layer discontinuous, and the concentration stress is decreased to avoid a crack formed on the solder resist layer or the copper wiring layer when doing thermal-cycle test.
Claims20
A semiconductor package comprising:
- a substrate having
- a dielectric layer having a first surface;
- a copper wiring layer formed on the first surface of the dielectric layer;
- a solder resist layer covering the copper wiring layer and having
- a chip area;
- an external area surrounding the chip area;
- and
- an annular opening formed on the external area, wherein a part of the copper wiring layer is exposed in the annular opening;
- a first chip mounted on the chip area of the solder resist layer and electrically connected to the substrate;
- and
- an encapsulation formed on the first chip and the external area of the substrate to encapsulate the first chip.
Dependencies are inferred from the claim text.