Semiconductor devices having a plurality of offsets in leads supporting stacked components and methods of manufacturing thereof

A semiconductor device, comprising:

• a substrate comprising a first lead and a second lead, wherein:
• the first lead comprises:
• a first lead terminal comprising a first outer side, a first inner side opposite to the first outer side, and a first lower side connecting the first outer side to the first inner side;
• a first lead step coupled to the first lead terminal and residing on a first plane;
• a first lead offset coupled to the first lead step;
• a second lead step coupled to the first lead offset and residing on a second plane that is different than the first plane;
• a second lead offset coupled to the second lead step;
• and
• a third lead step coupled to the second lead offset and residing on a third plane that is different than the second plane;
• the second lead comprises:
• a second lead terminal comprising a second outer side, a second inner side opposite to the second outer side, and a second lower side connecting the second outer side to the second inner side;
• a fourth lead step coupled to the second lead terminal and residing on a fourth plane;
• a third lead offset coupled to the fourth lead step;
• a fifth lead step coupled to the third lead offset and residing on a fifth plane that is different than the fourth plane;
• a fourth lead offset coupled to the fifth lead step;
• and
• a sixth lead step coupled to the fourth lead offset and residing on a sixth plane that is different than the fifth plane;
• a first electronic component coupled to the first lead;
• a second electronic component coupled to the second lead;
• and
• an encapsulant encapsulating the first electronic component, the second electronic component, and portions of the substrate, wherein:
• the encapsulant comprises an encapsulant first side, an encapsulant second side opposite to the encapsulant first side, and an encapsulant lateral side connecting the encapsulant first side to the encapsulant second side;
• and
• the first lower side of the first lead terminal and the second lower side of the second lead terminal are exposed from and coplanar with the encapsulant first side.

A method of manufacturing a semiconductor device, comprising:

• providing a substrate comprising leads, the leads comprising:
• lead terminals each comprising an outer side, an inner side opposite to the outer side, and a lower side connecting the outer side to the inner side;
• lead steps;
• and
• lead offsets extending between the lead steps so that at least some lead steps reside on different planes;
• coupling a first electronic component to a first lead step side, the first electronic component comprising:
• a first electronic component first side;
• and
• a first electronic component second side opposite to the first electronic component first side;
• coupling a second electronic component to a second lead step side, the second electronic component comprising:
• a second electronic component first side;
• and
• a second electronic component second side opposite to the second electronic component first side;
• and
• providing an encapsulant encapsulating the first electronic component, the second electronic component, and portions of the substrate,
• wherein:
• the encapsulant comprises a first side;
• the lower sides of the lead terminals are exposed from and coplanar with the first side of the encapsulant;
• and
• the encapsulant encapsulates the inner sides of the lead terminals.

A semiconductor device, comprising:

• a substrate comprising leads, the leads comprising:
• lead terminals;
• lead steps;
• and
• lead offsets extending between the lead steps so that at least some lead steps reside on different planes;
• a first electronic component coupled to a first lead step side, the first electronic component comprising:
• a first electronic component first side comprising a first active side;
• and
• a first electronic component second side opposite to the first electronic component first side;
• a second electronic component coupled to a second lead step side, the second electronic component comprising:
• a second electronic component first side comprising a second active side;
• and
• a second electronic component second side opposite to the second electronic component first side;
• conductive bumps comprising a first conductive bump and a second conductive bump;
• a third electronic component coupled to a third lead step side and interposed between the first electronic component and the second electronic component;
• and
• an encapsulant encapsulating the first electronic component, the second electronic component, the first conductive bump, the second conductive bump, the third electronic component, and portions of the substrate,
• wherein:
• the first active side faces and is connected to the first lead step side with the first conductive bump;
• the second active side faces and is connected to the second lead step side with the second conductive bump;
• and
• the lead terminals are exposed from a first side of the encapsulant.

A semiconductor device, comprising:

• a substrate comprising leads, the leads comprising:
• lead terminals;
• lead steps;
• and
• lead offsets extending between the lead steps so that at least some lead steps reside on different planes;
• a first electronic component coupled to a first lead step side, the first electronic component comprising:
• a first electronic component first side comprising a first active side;
• and
• a first electronic component second side opposite to the first electronic component first side;
• a second electronic component coupled to a second lead step side, the second electronic component comprising:
• a second electronic component first side comprising a second active side;
• and
• a second electronic component second side opposite to the second electronic component first side;
• conductive bumps comprising a first conductive bump and a second conductive bump;
• and
• an encapsulant encapsulating the first electronic component, the second electronic component, the first conductive bump, the second conductive bump, and portions of the substrate,
• wherein:
• the first active side faces and is connected to the first lead step side with the first conductive bump;
• the second active side faces and is connected to the second lead step side with the second conductive bump;
• the lead terminals are exposed from a first side of the encapsulant;
• the lead terminals downwardly extend from bottom sides of outermost lead steps;
• the lead terminals each comprise:
• an outer edge exposed from and coplanar with a third side of the encapsulant;
• an inner edge opposite to the outer edge;
• and
• a lower side;
• the encapsulant encapsulates each of the inner edges;
• and
• the lower side of each lead terminal is exposed from and coplanar with the first side of the encapsulant.

A semiconductor device, comprising:

• a substrate comprising leads, the leads comprising:
• lead terminals;
• lead steps;
• and
• lead offsets extending between the lead steps so that at least some lead steps reside on different planes;
• a first electronic component coupled to a first lead step side, the first electronic component comprising:
• a first electronic component first side comprising a first active side;
• and
• a first electronic component second side opposite to the first electronic component first side;
• a second electronic component coupled to a second lead step side, the second electronic component comprising:
• a second electronic component first side comprising a second active side;
• and
• a second electronic component second side opposite to the second electronic component first side;
• conductive bumps comprising a first conductive bump and a second conductive bump;
• and
• an encapsulant encapsulating the first electronic component, the second electronic component, the first conductive bump, the second conductive bump, and portions of the substrate,
• wherein:
• the first active side faces and is connected to the first lead step side with the first conductive bump;
• the second active side faces and is connected to the second lead step side with the second conductive bump;
• the lead terminals are exposed from a first side of the encapsulant;
• the substrate comprises a paddle having a paddle top side, a paddle bottom side opposite to the paddle top side, and a paddle extension with an extension terminal;
• the first electronic component is coupled to the paddle top side;
• the second electronic component is coupled to the paddle bottom side;
• and
• the extension terminal is exposed from the first side of the encapsulant.