3D semiconductor device and structure with metal layers and a connective path

A 3D semiconductor device, the device comprising:

• a first level comprising a plurality of first metal layers;
• a second level,
• wherein said second level overlays said first level,
• wherein said second level comprises at least one single crystal silicon layer,
• wherein said second level comprises a plurality of transistors,
• wherein each transistor of said plurality of transistors comprises a single crystal channel,
• wherein said second level comprises a plurality of second metal layers,
• wherein said plurality of second metal layers comprise interconnections between said transistors of said plurality of transistors, and
• wherein said second level is overlaid by a first isolation layer;
• and
• a connective path between said plurality of transistors and said plurality of first metal layers,
• wherein said connective path comprises a via disposed through at least said single crystal silicon layer,
• wherein said via is part of connective path between at least one of said transistors to at least one of said first metal layers, and
• wherein said transistors of said plurality of transistors are aligned to said first metal layers with a less than 40 nm alignment error.

A 3D semiconductor device, the device comprising:

• a first level comprising a plurality of first metal layers;
• a second level,
• wherein said second level overlays said first level,
• wherein said second level comprises at least one single crystal silicon layer,
• wherein said second level comprises a plurality of transistors,
• wherein each transistor of said plurality of transistors comprises a single crystal channel,
• wherein said second level comprises a plurality of second metal layers,
• wherein said plurality of second metal layers comprise interconnections between said transistors of said plurality of transistors, and
• wherein said second level is overlaid by a first isolation layer;
• and
• a connective path between said plurality of transistors and said plurality of first metal layers,
• wherein said connective path comprises a via disposed through at least said single crystal silicon layer, and
• wherein said device comprise plurality of capacitors.