3D stack of accelerator die and multi-core processor die

A system comprising:

• a memory;
• a processor die comprising a plurality of processor cores and a cache, wherein the processor die is coupled to the memory, wherein the plurality of processor cores is arranged on either side of the cache;
• an accelerator die stacked on the processor die, wherein the accelerator die is positioned directly above the cache;
• and
• a communication interface to allow the processor die to communicate with another device.

An apparatus comprising:

• a processor die comprising a plurality of processor cores and a cache, wherein the plurality of processor cores is arranged on either side of the cache;
• an accelerator die stacked on the processor die, wherein the accelerator die is positioned directly above the cache, wherein the accelerator die includes a first interconnect fabric, wherein the processor die includes a second interconnect fabric, wherein the first interconnect fabric is coupled to the second interconnect fabric via copper-to-copper bonding, and wherein the accelerator die includes majority gates or minority gates;
• a first passive silicon adjacent to the accelerator die and over a first set of processor cores of the plurality of processor cores;
• and
• a second passive silicon adjacent to the accelerator die and over a second set of processor cores of the plurality of processor cores, wherein the first set of processor cores and the second set of processor cores are on either side of the cache of the processor die.