Semiconductor package and method of fabricating the same

A semiconductor package, comprising:

• a package substrate;
• a redistribution substrate on the package substrate, the redistribution substrate having a chip region and an edge region around the chip region;
• a first semiconductor chip on the chip region of the redistribution substrate;
• a second semiconductor chip on the chip region of the redistribution substrate and spaced apart from the first semiconductor chip, the second semiconductor chip including a plurality of memory chips that are vertically stacked;
• a molding layer on the redistribution substrate, the molding layer covering the first semiconductor chip and the second semiconductor chip;
• a plurality of first connection terminals between the redistribution substrate and the first semiconductor chip and between the redistribution substrate and the second semiconductor chip;
• a plurality of second connection terminals between the package substrate and the redistribution substrate;
• and
• a thermal radiation structure on the package substrate, the thermal radiation structure covering the redistribution substrate, the first semiconductor chip, and the second semiconductor chip,
• wherein the redistribution substrate includes:
• a plurality of dielectric layers that are vertically stacked;
• a plurality of first redistribution patterns on the chip region and in each of the dielectric layers,
• wherein a second redistribution pattern on the edge region and in at least one of the dielectric layers, the second redistribution pattern having a sidewall vertically aligned with sidewalls of the dielectric layers, and
• wherein the sidewall of the second redistribution test pattern is laterally spaced apart from the first connection terminals.

A method of fabricating a semiconductor package, the method comprising:

• providing a carrier substrate that includes a plurality of chip regions and a scribe line region between the chip regions;
• forming a redistribution substrate including a plurality of redistribution layers vertically stacked on the carrier substrate, each of the redistribution layers including a dielectric layer and a plurality of redistribution patterns;
• mounting a semiconductor chip on the redistribution substrate;
• forming a molding layer that covers the semiconductor chip;
• and
• cutting the molding layer and the redistribution substrate along the scribe line region,
• wherein at least one of the redistribution layers includes:
• a plurality of redistribution test patterns on the chip region;
• and
• a plurality of test pads connected to the redistribution test patterns and provided on the scribe line region, and
• wherein forming the redistribution substrate includes performing a test process on at least one of the redistribution layers via the test pads, and
• wherein the test process is performed before the semiconductor chip is mounted on the redistribution substrate.