Methods of forming metal gate spacer

A semiconductor structure, comprising:

• an isolation feature disposed over a substrate;
• a high-k metal gate structure (HKMG), wherein an entirety of the HKMG is disposed directly over the isolation feature;
• a gate spacer layer disposed along a bottom portion of a sidewall of the HKMG, wherein a top portion of the sidewall of the HKMG is free of the gate spacer layer;
• a dielectric layer disposed over the top portion of the sidewall of the HKMG and across a top surface of the gate spacer, wherein a bottom portion of the dielectric layer is separated from the bottom portion of the sidewall of the HKMG by the gate spacer layer;
• an interlayer dielectric (ILD) layer disposed over the isolation feature;
• and
• a conductive feature disposed adjacent to the HKMG, wherein the ILD layer separates the conductive feature from the dielectric layer.

A semiconductor structure, comprising:

• a semiconductor fin;
• an isolation feature disposed adjacent to the semiconductor fin;
• a first metal gate structure disposed over the semiconductor fin, wherein a bottom surface of the first metal gate structure extends entirely over a top surface of the semiconductor fin;
• a second metal gate structure disposed entirely over the isolation feature;
• a spacer layer disposed along a bottom portion of a sidewall of the second metal gate structure, wherein a sidewall of the first metal gate structure and a top portion of the sidewall of the second metal gate structure are free of the spacer layer;
• an etch-stop layer (ESL) disposed along the sidewall of the first metal gate structure and the sidewall of the second metal gate structure, wherein the bottom portion of the sidewall of the second metal gate structure is separated from the ESL by the spacer layer;
• and
• an air gap disposed between the sidewall of the first metal gate structure and the ESL,
• wherein the air gap extends along the sidewall of the first metal gate structure to expose the semiconductor fin.