US 11,694,932 B2 · Array of vertical transistors, an array of memory cells comprising an array of vertical transistors, and a method used in forming an array of vertical transistors

Abstract

A method used in forming an array of vertical transistors comprises forming laterally-spaced vertical projections that project upwardly from a substrate in a vertical cross-section. The vertical projections individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. First gate insulator material is formed along opposing sidewalls of the channel region in the vertical cross-section. One of (a) or (b) is formed over opposing sidewalls of the first gate insulator material in the vertical cross-section, where (a): conductive gate lines that are horizontally elongated through the vertical cross-section; and (b): sacrificial placeholder gate lines that are horizontally elongated through the vertical cross-section. The one of the (a) or the (b) laterally overlaps the upper source/drain region and the lower source/drain region. The first gate insulator material has a top that is below a top of the channel region and has a bottom that is above a bottom of the channel region. An upper void space is laterally between the one of the (a) or the (b) and both of the upper source/drain region and the channel region. A lower void space is laterally between the one of the (a) or the (b) and both of the lower source/drain region and the channel region. Second gate insulator material is formed in the upper and lower void spaces. Other embodiments, including structure independent of method, are disclosed.

Claims27

Dependent claims

A vertical transistor comprising:

an upper source/drain region, a channel region, and a lower source/drain region;
the channel region comprising an upper portion, an intervening portion, and a lower portion;
insulative material along a sidewall of the channel region, a sidewall of the upper source/drain region, and a sidewall of the lower source/drain region;
conductive material adjacent the insulative material, the conductive material vertically extending from a level corresponding to an upper portion of the lower source/drain region to a level corresponding to a lower portion of the upper source/drain region;
and
the insulative material being thicker at both the level corresponding to the upper portion of the lower source/drain region and the level corresponding to the lower portion of the upper source/drain region than at a level corresponding to the intervening portion of the channel region.

3 more elements

Dependencies are inferred from the claim text.

Array of vertical transistors, an array of memory cells comprising an array of vertical transistors, and a method used in forming an array of vertical transistors

Life of this patent

Array of vertical transistors, an array of memory cells comprising an array of vertical transistors, and a method used in forming an array of vertical transistors

Life of this patent

Abstract

Claims27