Barrier free interface between beol interconnects
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsiu-Wen Hsueh, Chii-Ping Chen, Po-Hsiang Huang, Ya-Ching Tseng
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Abstract
The present disclosure relates an integrated chip. The integrated chip includes a first interconnect disposed within an inter-level dielectric (ILD) structure over a substrate. A barrier layer is disposed along sidewalls of the ILD structure. The barrier layer has sidewalls defining an opening over the first interconnect. A second interconnect is disposed on the barrier layer. The second interconnect extends through the opening in the barrier layer and to the first interconnect.
Claims20
An integrated chip, comprising:
- a first interconnect disposed between lower sidewalls of an inter-level dielectric (ILD) structure over a substrate, the first interconnect having sidewalls that contact the lower sidewalls of the ILD structure along interfaces as viewed along a cross-sectional view;
- a barrier layer disposed along upper sidewalls of the ILD structure and having sidewalls defining an opening over the first interconnect;
- a second interconnect disposed on the barrier layer, wherein the second interconnect extends through the opening in the barrier layer and to the first interconnect and wherein a bottommost surface of the barrier layer laterally extends past an interior sidewall of the barrier layer that faces the second interconnect;
- and
- wherein opposing outermost edges of a bottommost surface of the second interconnect are laterally aligned with the interfaces.
An integrated chip, comprising:
- a first interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate;
- a second ILD layer disposed over the first ILD layer;
- a barrier layer extending along a sidewall of the second ILD layer and along an upper surface of the first ILD layer, wherein the barrier layer comprises a vertically extending segment disposed along the sidewall of the second ILD layer and a horizontally extending segment protruding outward from the vertically extending segment towards the first interconnect;
- a first liner disposed on the barrier layer;
- and
- a second liner disposed on the first liner and surrounding a conductive interior, wherein the first liner extends completely through the barrier layer to physically contact the first interconnect, and wherein the second liner has a bottommost surface that contacts the first liner along an interface that continuously extends between outermost sidewalls of the second liner, an entirety of the interface being vertically above an upper surface of the barrier layer that is directly below the conductive interior.
A method of forming an integrated chip, comprising:
- forming a first interconnect within a first inter-level dielectric (ILD) layer over a substrate;
- forming a second ILD layer over the first ILD layer;
- patterning the second ILD layer to form sidewalls defining an interconnect opening that exposes an upper surface of the first interconnect;
- forming a blocking layer onto the upper surface of the first interconnect, wherein the blocking layer is laterally separated from the sidewalls of the second ILD layer by a space that exposes outermost sidewalls of the blocking layer;
- forming a barrier layer within the interconnect opening;
- removing the blocking layer to expose the upper surface of the first interconnect;
- and
- forming a second interconnect within the interconnect opening.
Dependencies are inferred from the claim text.