US 11,694,754 B2Granted

Semiconductor memory device that provides a memory die

AssigneeKioxia Corporation

InventorYuzuru Shibazaki

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Abstract

ABSTRACT A semiconductor memory device provides a first memory cell array including a plurality of first memory blocks, a second memory cell array comprising a plurality of second memory blocks, and a voltage supply line electrically connected to the plurality of first memory blocks and the plurality of second memory blocks. Moreover, this semiconductor memory device is configured to execute a write operation. At a first timing of this write operation, the voltage supply line is not electrically continuous with the first and second memory blocks. Moreover, a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first and second memory blocks is larger than a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first memory block.

Claims18

Dependent claims

A semiconductor memory device comprising a memory die,

the memory die comprising:
a first memory cell array that comprises a plurality of first memory blocks;
a second memory cell array that comprises a plurality of second memory blocks;
and
a first voltage supply line which is electrically connected to the plurality of first memory blocks and the plurality of second memory blocks, wherein
the semiconductor memory device is configured to execute a write operation,
at a first timing of the write operation, the first voltage supply line is not electrically continuous with any one of the plurality of first memory blocks and the plurality of second memory blocks,
in the case of the write operation being executed on any one of the plurality of first memory blocks and not being executed on any one of the plurality of second memory blocks, the first voltage supply line is supplied with a first voltage at the first timing,
in the case of the write operation being executed on any one of the plurality of first memory blocks and being executed on any one of the plurality of second memory blocks, the first voltage supply line is supplied with a second voltage at the first timing, and
the second voltage being is larger than the first voltage.

7 more elements

A semiconductor memory device comprising a memory die,

the memory die comprising:
a first memory cell array that comprises a plurality of first memory blocks;
a second memory cell array that comprises a plurality of second memory blocks;
a first voltage supply line which is electrically connected to the plurality of first memory blocks and the plurality of second memory blocks;
a first capacitor which is electrically connected to the first voltage supply line;
and
a first transistor which is provided in a current path between the first voltage supply line and the first capacitor.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/469,095Filed 8 Sep 2021
Priority: JP 2020-2043779 Dec 2020
Published: US 2022/0180945 A19 Jun 2022
Granted: 4 Jul 2023
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 16/30
Auxiliary circuits, e.g. for writing into memory: power supply circuits
G11C 16/32
Auxiliary circuits, e.g. for writing into memory: timing circuits
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 16/08
Auxiliary circuits, e.g. for writing into memory: address circuits; Decoders; Word-line control circuits