Memory cell sensing
AssigneeMicron Technology, Inc.
InventorJun Xu
Life of this patent
Estimating the term…
Abstract
Memory might include a controller configured to cause the memory to capacitively couple a first voltage level from a voltage node to a node of a sense circuit, selectively discharge the node of the sense circuit through a memory cell, measure a current demand of the voltage node while selectively discharging the node of the sense circuit through the memory cell, determine a second voltage level in response to the measured current demand, isolate the node of the sense circuit from the memory cell, capacitively couple the second voltage level from the voltage node to the node of the sense circuit, and determine a data state of the memory cell in response to a voltage level of the node of the sense circuit while capacitively coupling the second voltage level to the node of the sense circuit.
Claims22
A memory, comprising:
- an array of memory cells;
- a sense circuit;
- a voltage node;
- and
- a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
- capacitively couple a first voltage level from the voltage node to a node of the sense circuit;
- selectively discharge the node of the sense circuit through a memory cell while capacitively coupling the first voltage level to the node of the sense circuit;
- measure a current demand of the voltage node while selectively discharging the node of the sense circuit through the memory cell;
- determine a second voltage level in response to the measured current demand;
- isolate the node of the sense circuit from the memory cell;
- capacitively couple the second voltage level from the voltage node to the node of the sense circuit after isolating the node of the sense circuit from the memory cell;
- and
- determine a data state of the memory cell in response to a voltage level of the node of the sense circuit while capacitively coupling the second voltage level to the node of the sense circuit.
A memory, comprising:
- an array of memory cells;
- a plurality of sense circuits, wherein each sense circuit of the plurality of sense circuits is selectively connected to a respective memory cell of a plurality of memory cells of the array of memory cells;
- a voltage node;
- and
- a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
- precharge a respective node of each sense circuit of the plurality of sense circuits to a first voltage level;
- capacitively couple a second voltage level from the voltage node to the respective node of each sense circuit of the plurality of sense circuits;
- for each sense circuit of the plurality of sense circuits, selectively discharge its respective node through its respective memory cell while capacitively coupling the second voltage level to its respective node;
- measure a current demand of the voltage node while capacitively coupling the second voltage level to the respective node of each sense circuit of the plurality of sense circuits and selectively discharging the respective node of each sense circuit of the plurality of sense circuits;
- determine a third voltage level in response to the measured current demand;
- for each sense circuit of the plurality of sense circuits, isolate its respective node from its respective memory cell;
- capacitively couple the third voltage level from the voltage node to the respective node of each sense circuit of the plurality of sense circuits while the respective node of each sense circuit of the plurality of sense circuits is isolated from its respective memory cell;
- and
- for each sense circuit of the plurality of sense circuits, determine a respective data state of its respective memory cell in response to a voltage level of its respective node while capacitively coupling the third voltage level to its respective node.
A memory, comprising:
- an array of memory cells;
- a sense circuit;
- a voltage node;
- and
- a controller for access of the array of memory cells, wherein the controller is configured to cause the memory to:
- apply a first voltage level to a first electrode of a capacitance of the sense circuit from the voltage node while a second electrode of the capacitance is connected to a memory cell of the array of memory cells;
- measure a current demand of the voltage node while applying the first voltage level to the first electrode of the capacitance and while the second electrode of the capacitance is connected to the memory cell;
- determine a second voltage level in response to the measured current demand;
- and
- apply the second voltage level to the first electrode of the capacitance from the voltage node while the second electrode of the capacitance is isolated from the memory cell.
Dependencies are inferred from the claim text.