Clock signal return scheme for data read in page buffer of memory device
AssigneeYangtze Memory Technologies Co., Ltd.
InventorShu Xie
Life of this patent
Estimating the term…
Abstract
In certain aspects, a circuit includes a page buffer including a plurality of portions, a clock path coupled to the plurality of portions of the page buffer, and a clock level set module coupled to the page buffer. Each of the portions is configured to sequentially receive a clock signal, and sequentially return a clock return signal in response to receiving the corresponding clock signal. The clock path is configured to merge the plurality of clock return signals. The clock level set module is configured to set a start level of a first clock return signal of the plurality of clock return signals based on a number of cycles in a first clock signal of the plurality of clock signals. The first clock return signal corresponds to the first clock signal.
Claims20
A circuit, comprising:
- a page buffer comprising a plurality of portions, each of the portions being configured to sequentially receive a clock signal, and sequentially return a clock return signal in response to receiving the corresponding clock signal;
- a clock path coupled to the plurality of portions of the page buffer and configured to merge the plurality of clock return signals;
- and
- a clock level set module coupled to the page buffer and configured to set a start level of a first clock return signal of the plurality of clock return signals based on a number of cycles in a first clock signal of the plurality of clock signals, the first clock return signal corresponding to the first clock signal.
A system, comprising:
- a memory device comprising a memory cell array configured to store data, and a peripheral circuit coupled to the memory cell array and configured to perform a read operation on the memory cell array to read the stored data, the peripheral circuit comprising:
- a page buffer comprising a plurality of portions, each of the portions being configured to sequentially receive a clock signal, and sequentially return a clock return signal in response to receiving the corresponding clock signal;
- a clock path coupled to the plurality of portions of the page buffer and configured to merge the plurality of clock return signals;
- and
- a clock level set module coupled to the page buffer and configured to set a start level of a first clock return signal of the plurality of clock return signals based on a number of cycles in a first clock signal of the plurality of clock signals, the first clock return signal corresponding to the first clock signal.
A method for operating a memory device comprising a page buffer, the method comprising:
- receiving a read instruction;
- obtaining an address of the page buffer in the read instruction;
- determining a parity of a number of cycles in a first clock signal based on the address, the first clock signal being received by a first portion of the page buffer;
- and
- setting a start level of a first clock return signal based on the parity, wherein the first clock return signal is returned by the first portion of the page buffer in response to receiving the first clock signal.
Dependencies are inferred from the claim text.