System and method for reading memory cells
AssigneeMicron Technology, Inc.
InventorsUmberto Di Vincenzo, Riccardo Muzzetto, Ferdinando Bedeschi
Life of this patent
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Abstract
A method, a circuit, and a system for reading memory cells. The method may include: applying a first voltage with a first polarity to a plurality of the memory cells; applying a second voltage with a second polarity to one or more of said plurality of the memory cells; applying at least a third voltage with the first polarity to one or more of said plurality of the memory cells; detecting electrical responses of memory cells to the first voltage, the second voltage, and the third voltage; and determining a logic state of respective memory cells based on the electrical responses of the memory cells to the first voltage, the second voltage, and the third voltage.
Claims20
A method, comprising:
- applying one or more first voltage pulses to a plurality of memory cells;
- applying one or more second voltage pulses to the plurality of memory cells;
- applying one or more third voltage pulses to the plurality of memory cells, wherein the application of the one or more second voltage pulses and the one or more third voltage pulses is based at least in part on a triggering event;
- and
- determining a logic state of respective memory cells from the plurality of memory cells based at least in part on a combined application of the one or more first voltage pulses, the one or more second voltage pulses, and the one or more third voltage pulses.
A method, comprising:
- applying one or more first voltage pulses to a plurality of memory cells;
- applying one or more second voltage pulses to the plurality of memory cells;
- applying one or more third voltage pulses to the plurality of memory cells;
- determining that a first portion of the plurality of memory cells is associated with a first logic state based at least in part on a first electrical response of the first portion of the plurality of memory cells to the one or more first voltage pulses;
- and
- determining a logic state of a remaining portion of respective memory cells from the plurality of memory cells based at least in part on a combined application of the one or more first voltage pulses, the one or more second voltage pulses, and the one or more third voltage pulses.
An apparatus, comprising:
- a plurality of memory cells;
- a memory controller coupled with the plurality of memory cells, the memory controller configured to cause the apparatus to:
- apply one or more first voltage pulses to the plurality of memory cells;
- apply one or more second voltage pulses to the plurality of memory cells;
- apply one or more third voltage pulses to the plurality of memory cells, wherein the application of the one or more second voltage pulses and the one or more third voltage pulses is based at least in part on a triggering event;
- and
- access circuitry configured to determine a logic state of respective memory cells from the plurality of memory cells based at least in part on a combined application of the one or more first voltage pulses, the one or more second voltage pulses, and the one or more third voltage pulses.
Dependencies are inferred from the claim text.