Semiconductor storage device
AssigneeKioxia Corporation
InventorKosuke Yanagidaira
Life of this patent
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Abstract
A semiconductor storage device includes a memory transistor and a word line connected to a gate electrode of the memory transistor. When a write sequence is interrupted before a k+1th verification operation is ended after a kth verification operation is ended in the nth write loop of the write sequence, a voltage equal to or higher than a verification voltage corresponding to a first verification operation in the nth write loop is supplied to the word line before start of the k+1th verification operation after resumption of the write sequence. A time from the resumption of the write sequence to the start of the k+1th verification operation is shorter than a time from start of the first verification operation to end of the kth verification operation in the nth write loop.
Claims11
A semiconductor storage device comprising:
- a memory transistor, and a word line connected to a gate electrode of the memory transistor,
- wherein the semiconductor storage device is configured to execute a write sequence in which a write loop is executed for the memory transistor multiple times,
- the write loop includes a program operation of supplying a program voltage to the word line, and at least one verification operation of supplying a verification voltage to the word line,
- when the write sequence is not interrupted between start and end of the write sequence, in an nth (where n is a natural number) write loop, the program operation is executed once, and the verification operation is executed m (where m is a natural number of 2 or more) times, and
- when the write sequence is interrupted before a k+1th verification operation is ended after a kth verification operation is ended in the nth write loop of the write sequence (where k is a natural number less than m), a voltage equal to or higher than the verification voltage corresponding to a first verification operation in the nth write loop is supplied to the word line before start of the k+1th verification operation after resumption of the write sequence, and
- a time from the resumption of the write sequence to the start of the k+1th verification operation is shorter than a time from a start of the first verification operation in the nth write loop to an end of the kth verification operation in the nth write loop.
A semiconductor storage device comprising:
- a memory transistor;
- a word line connected to a gate electrode of the memory transistor;
- and
- a sequencer circuit configured to output control signals to execute a write sequence in which a write loop is executed for the memory transistor multiple times, the write loop including a program operation of supplying a program voltage to the word line, and at least one verification operation of supplying a verification voltage to the word line, wherein
- when the write sequence is interrupted between start and end of the write sequence during execution of a write loop in which at least two verification operations are ended but before a next verification operation after said at least two verification operations is ended, a voltage equal to or higher than the verification voltage corresponding to a first verification operation in the write loop is supplied to the word line before start of said next verification operation after resumption of the write sequence, and
- a time from the resumption of the write sequence to the start of the next verification operation is shorter than a time taken to carry out said at least two verification operations that ended when the write sequence was interrupted.
Dependencies are inferred from the claim text.