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US 11,694,745 B1Granted
SRAM with small-footprint low bit-error-rate readout
AssigneeGigajot Technology, Inc.
InventorDexue Zhang
Life of this patent
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Abstract
Conventional SRAM sense-amplifiers are replaced by small-footprint keeper circuits that enable single-ended SRAM readout without bitline precharge, simplifying and relaxing the timing of SRAM cell access and bitline sampling operations and thus enabling potentially faster readout operation and/or lower bit error rate.
Claims21
An imaging integrated-circuit (IC), comprising:
- a bit line;
- a static random access memory (SRAM) cell to drive, according to a logic state of a data bit stored therein, a read-out signal onto the bit line throughout a first interval;
- an inverter circuit having a single-ended input coupled to the bit line to receive the readout-signal via and an output to generate a data output signal having a logic state according to the logic state of the data bit stored within the SRAM cell;
- and
- transistor circuitry to latch the data output signal at the output of the inverter circuit throughout a second interval that commences prior to conclusion of the first interval, the transistor circuitry including first and second transistors having respective gate terminals coupled to the output of the inverter circuit to switchably couple the bit line to either a first voltage node or a second voltage node, respectively, according to a voltage level of the data output signal and throughout the second interval.
2 more elements
A method of operation within an imaging integrated-circuit (IC), the method comprising:
- enabling a static random access memory (SRAM) cell to drive, according to a logic state of a data bit stored within the SRAM cell, a read-out signal onto a bit line throughout a first interval;
- generating, at an output of an inverter circuit having a single-ended input coupled to the bit line, a data output signal having a logic state according to the logic state of the data bit stored within the SRAM cell;
- and
- throughout a second interval that commences prior to conclusion of the first interval, latching the data output signal at the output of the inverter circuit by coupling the bit line to either (i) a first voltage node via a first transistor having a gate terminal coupled to the output of the inverter circuit, or (ii) a second voltage node via a second transistor having a gate terminal coupled to the output of the inverter circuit.
1 more element
An imaging integrated-circuit (IC), comprising:
- a bit line;
- a static random access memory (SRAM) cell to drive, according to a logic state of a data bit stored therein, a read-out signal onto the bit line throughout a first interval;
- an inverter circuit having a single-ended input coupled to the bit line to receive the readout-signal via and an output to generate a data output signal having a logic state according to the logic state of the data bit stored within the SRAM cell;
- and
- means for latching the data output signal at the output of the inverter circuit throughout a second interval that commences prior to conclusion of the first interval, the means for latching including first and second transistors having respective gate terminals coupled to the output of the inverter circuit to switchably couple the bit line to either a first voltage node or a second voltage node, respectively, according to a voltage level of the data output signal and throughout the second interval.
2 more elements
Dependencies are inferred from the claim text.