Chip and associated chip system
AssigneeRealtek Semiconductor Corp.
InventorChing-Sheng Cheng
Life of this patent
Estimating the term…
Abstract
A chip system includes a first chip, a first DRAM, a second chip and a second DRAM. The first chip includes a first DRAM controller and a first serial transmission interface. The first DRAM is coupled to the first DRAM controller. The second chip includes a second DTAM controller and a second serial transmission interface. The second serial transmission interface is coupled to the first serial transmission interface. The second DRAM is coupled to the second DRAM controller. When the first chip intends to store first data and second data, the first chip stores the first data into the first DRAM via the first DRAM controller, and transmits the second data to the second chip via the first serial transmission interface; and the second chip stores the second data into the second DRAM via the second DRAM controller.
Claims13
A chip system, comprising:
- a first chip, comprising a first dynamic random access memory (DRAM) controller and a first serial transmission interface;
- a first DRAM, coupled to the first DRAM controller of the first chip;
- a second chip, comprising a second DRAM controller and a second serial transmission interface, wherein the second serial transmission interface is coupled to the first serial transmission interface;
- and
- a second DRAM, coupled to the second DRAM controller of the second chip;
- wherein when the first chip intends to store first data and second data, the first chip stores the first data into the first DRAM via the first DRAM controller, and transmits the second data to the second chip via the first serial transmission interface;
- and the second chip stores the second data into the second DRAM via the second DRAM controller.
A chip, comprising:
- a core circuit;
- a dynamic random access memory (DRAM) controller, coupled to a DRAM;
- and
- a serial transmission interface, coupled to another chip;
- wherein when the core circuit intends to store first data and second data, the core circuit stores the first data into the DRAM via the DRAM controller, and transmits the second data to said another chip via the serial transmission interface, such that said another chip stores the second data into another DRAM which is accessible to said another chip;
- wherein the chip further comprises a memory, the memory comprises a lookup table, and the lookup table records that an address of the first data corresponds to the DRAM or the chip, and an address of the second data corresponds to said another chip.
A chip, comprising:
- a core circuit;
- a dynamic random access memory (DRAM) controller, coupled to a DRAM;
- and
- a serial transmission interface, coupled to another chip;
- wherein when the core circuit intends to store first data and second data, the core circuit stores the first data into the DRAM via the DRAM controller, and transmits the second data to said another chip via the serial transmission interface, such that said another chip stores the second data into another DRAM which is accessible to said another chip;
- wherein when the core circuit intends to read the first data and the second data, the core circuit read the first data from the DRAM via the DRAM controller;
- and the core circuit transmits a read command to said another chip via the serial transmission interface, wherein the read command comprises an address of the second data, such that said another chip reads the second data from said another DRAM.
Dependencies are inferred from the claim text.