Internal voltage generation circuit and semiconductor memory apparatus including the same

A semiconductor memory apparatus comprising:

• a plurality of plane regions each including a memory bank;
• an enable control circuit configured to generate a final enable signal in response to an enable signal by delaying an activation time point of the final enable signal by a reset time from the time point when the enable signal is inactivated;
• a start-up control circuit configured to perform a reset operation during the reset time, and generate a start-up signal based on the final enable signal;
• a reference voltage generation circuit configured to generate a reference voltage based on the start-up signal;
• a current generation circuit configured to generate at least one reference current based on the reference voltage;
• and
• a plurality of voltage generation circuits corresponding to the plurality of plane regions, respectively, and configured to generate a plurality of internal voltages based on the at least one reference current.