Memory device, memory system including memory device, and method of operating memory device
AssigneeSK hynix Inc.
InventorJong Wook Kim
Life of this patent
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Abstract
A memory device, a memory system including the memory device, and a method of operating the memory device are described. The memory device includes a memory cell array including a plurality of planes, a peripheral circuit configured to perform a read operation including a channel initialization operation on a selected memory block among a plurality of memory blocks included in each of the plurality of planes, and a control logic configured to control the peripheral circuit to perform the read operation including the channel initialization operation, and the control logic sets an activation time of the channel initialization operation based on an read mode of the read operation.
Claims13
A memory device comprising:
- a memory cell array including a plurality of planes;
- a peripheral circuit configured to perform a read operation including a channel initialization operation on a selected memory block among a plurality of memory blocks included in each of the plurality of planes, wherein the channel initialization operation is performed to remove hot holes remaining in a channel of the selected memory block;
- and
- control logic configured to control the peripheral circuit to perform the read operation including the channel initialization operation,
- wherein the control logic determines whether a single plane read operation or a multi-plane read operation is performed based on a read mode of the read operation, and sets an activation time of the channel initialization operation of the read operation according to a determination result, and
- wherein in the single plane read operation, one plane is selected among the plurality of planes and the single read operation is performed thereon, and in the multi-plane read operation, at least two planes are selected together among the plurality of planes and the multi-read read operation is performed thereon, and read operation periods corresponding to the at least two planes overlap each other during the multi-plane read operation.
A method of operating a memory device, the method comprising:
- determining a read mode of a read operation based on a command received externally from the memory device;
- setting an activation time of a channel initialization operation based on the determined read mode;
- performing the channel initialization operation to remove hot holes remaining in a channel of a selected memory block during the activation time;
- and
- applying a read voltage to the selected memory block after performing the channel initialization operation,
- wherein determining the read mode comprises determining whether the command corresponds to a single plane read operation or a multi-plane read operation, and
- wherein in the single plane read operation, one plane is selected among the plurality of planes and the single read operation is performed thereon, and in the multi-plane read operation, at least two planes are selected together among the plurality of planes and multi—the read operation is performed thereon, and read operation periods corresponding to the at least two planes overlap each other during the multi-plane read operation.
A memory system comprising:
- a memory device including a plurality of semiconductor memories;
- and
- a memory controller configured to control a read operation of the memory device based on a read command received externally from the memory system,
- wherein the memory controller determines whether the read operation is an interleave read operation, a cache read operation, or a normal read operation, where the normal read operation is different from the interleave read operation or the cache read operation, based on the read command, and sets an activation time of a channel initialization operation of the read operation according to a determination result,
- wherein when the read operation is determined as the interleave read operation or the cache read operation, the memory controller sets the activation time of the channel initialization operation to a first time, and
- when the read operation is determined as the normal read operation, the activation time of the channel initialization operation is set to a second time shorter than the first time.
Dependencies are inferred from the claim text.