Write scheme for multi-element gain ferroelectric memory bit-cell with plate-line parallel to word-line to minimize write disturb effects

An apparatus comprising:

• a multi-element gain bit-cell comprising:
• a first capacitor having non-linear polar material, the first capacitor having a first terminal coupled to a node and a second terminal coupled to a first plate-line;
• a second capacitor comprising the non-linear polar material, the second capacitor having a first terminal coupled to the node and a second terminal coupled to a second plate-line;
• and
• two transistors connected to the node, wherein a first transistor of the two transistors is controlled by a voltage on the node, while a second transistor of the two transistors is controlled by a word-line, and wherein the second transistor is coupled to a bit-line;
• and
• one or more circuitries to control the bit-line, word-line, the first plate-line, and the second plate-line to perform a write operation on the multi-element gain bit-cell.

A system comprising:

• a processor circuitry to execute one or more instructions;
• a memory coupled to the processor circuitry, wherein the memory is to store the one or more instructions;
• a communication interface to allow the processor circuitry to communicate with another device, wherein the memory includes:
• a first node;
• a second node;
• a first capacitor comprising non-linear polar material, the first capacitor having a first terminal coupled to the first node and a second terminal coupled to a first plate-line;
• a second capacitor comprising the non-linear polar material, the second capacitor having a first terminal coupled to the first node and a second terminal coupled to a second plate-line;
• a first transistor coupled to the first node and a bit-line, wherein the first transistor is controllable by a word-line, and wherein the first plate-line and the second plate-line are parallel to the word-line;
• a second transistor having a gate terminal coupled to the first node, and a source terminal coupled to a sense-line and a drain terminal coupled to the second node;
• and
• one or more circuitries to boost the word-line during a write operation or a read operation.