Acceleration of in-memory-compute arrays

A method comprising:

• during a series of clock cycles, routing, by an in-memory compute circuit, a plurality of groups of input values that include digital data to different ones of a set of respective rows of the in-memory compute circuit, wherein the routing includes:
• routing a first group of input values to a first subset of the set of respective rows in a first clock cycle;
• and
• routing a second group of input values to a second subset of the set of respective rows in a second clock cycle that is subsequent to the first clock cycle;
• and
• during a subsequent clock cycle following the series of clock cycles:
• combining the groups of input values with a set of weight values stored in the set of respective rows to generate a set of products;
• and
• combining the set of products to generate an accumulated output value.

An image processing circuit comprising:

• a memory buffer circuit including a plurality of memory ranges that are configured to return a portion of stored data concurrently;
• a memory access circuit configured to distribute pixel data of a digitized image among the plurality of memory ranges;
• and
• an in-memory compute circuit, including sets of rows of memory cells, and configured to:
• receive a plurality of weight values to be stored in memory cells of at least a portion of the sets of rows;
• during a series of clock cycles, route groups of the pixel data to the sets of rows, including:
• routing a first group of pixel data to a first subset of the sets of rows in a first clock cycle of the series;
• and
• routing a second group of pixel data to a second subset of the sets of rows in a second clock cycle of the series, subsequent to the first clock cycle;
• and
• during a subsequent clock cycle following the series of clock cycles:
• generate a set of products using the groups of the pixel data and the received weight values;
• and
• generate an accumulated output value by combining a subset of the set of products.