Systems and methods for increasing a pulse width modulation frequency while preserving resolution

A method comprising:

• receiving a brightness code having a bit depth corresponding to a baseline resolution for a pulse width modulation system using a first counter clock frequency and a first pulse width modulation (PWM) clock frequency;
• dividing the brightness code by a value M using division circuitry to obtain a divided brightness code, wherein the value M is a positive integer;
• adding a remainder of the division to the divided brightness code;
• comparing the divided brightness code to a count of a counter clock having the first counter clock frequency over a first PWM clock having a second PWM clock frequency equal to the value M times the first PWM clock frequency;
• and
• providing a pulse width modulation PWM signal to cause a light emitting element to emit light during the first PWM clock while the count is lower than the divided brightness code.

Pulse width modulation (PWM) backlight control circuitry comprising:

• division circuitry configured to divide a PWM brightness code by a value M to obtain a divided brightness code, wherein the value M is a positive integer;
• adder circuitry configured to add a remainder of the division to the divided brightness code to obtain a duty cycle signal;
• a counter configured to count certain edges of a counter clock having a first frequency over a period corresponding to one clock cycle of a PWM clock, wherein the PWM clock has a second frequency that is equal to M times a third frequency corresponding to a baseline PWM clock that, when used with the counter clock having the first frequency, would result in a baseline PWM resolution;
• a digital comparator configured to compare the count of the certain edges of the counter clock to the duty cycle signal and output a reset signal when the count of the certain edges of the counter clock exceeds a value of the duty cycle signal;
• and
• a latch configured to output a PWM signal that causes a light emitting element to emit light when the latch is set by a certain edge of the PWM clock and to stop emitting light when the latch is reset by the reset signal;
• wherein the adder circuitry is configured to add the remainder to the divided brightness code to cause the duty cycle signal to have an average resolution over M PWM clock cycles that is equivalent to the baseline PWM resolution.