Gate driver and electroluminescent display apparatus including the same
AssigneeLG Display Co., Lid.
InventorSung Wook Chang
Life of this patent
Estimating the term…
Abstract
A gate driver includes a plurality of gate stages. Each of the plurality of gate stages includes a carry generating circuit outputting a second carry signal having a phase which is later than a phase of a first carry signal, on the basis of a first clock signal and a second clock signal having different phases and a scan generating circuit outputting a scan signal having a phase which differs from phases of the first and second carry signals, on the basis of the first clock signal, the second clock signal, and the first carry signal. Each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal may be a P-type pulse, and the scan signal may be an N-type pulse.
Claims25
A gate driver including a plurality of gate stages, each of the plurality of gate stages comprising:
- a carry generating circuit outputting a second carry signal having a phase which is later than a phase of a first carry signal, on the basis of a first clock signal and a second clock signal having different phases and the first carry signal synchronized with a pulse of one of the first clock signal and the second clock signal;
- and
- a scan generating circuit outputting a scan signal having a phase which differs from phases of the first carry signal and the second carry signal, on the basis of the first clock signal, the second clock signal, and the first carry signal,
- wherein each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal is a P-type pulse where a voltage of a pulse interval is lower than a voltage of a non-pulse interval, and
- the scan signal is an N-type pulse where the voltage of the pulse interval is higher than the voltage of the non-pulse interval.
A gate driver including a plurality of gate stages for driving a plurality of gate lines of a display panel, each gate stage connected to a respective gate line connected to one or more transistors in the display panel, a gate stage comprising:
- a carry generating circuit including a set of transistors of a first type, the carry generating circuit configured to receive a first clock signal, a second clock signal, and a first carry signal from a previous gate stage and generate a second carry signal for a next gate stage, a pulse interval of the second carry signal later than a pulse interval of the first carry signal;
- and
- a scan generating circuit including another set of transistors of the first type, the scan generating circuit configured to receive the first clock signal, the second clock signal, and the first carry signal and generate a scan signal for supply to the one or more transistors of a second type in the display panel,
- wherein pulse intervals of the first carry signal, the first clock signal, and the second clock signal are configured to turn on one or more transistors of the first type in the carry generating circuit and the scan generating circuit at a first logic state, and wherein the scan signal is configured to turn on the one or more transistors of the second type in the display panel at a second logic state.
Dependencies are inferred from the claim text.