Shift register unit, driving method thereof, and gate driving circuit

A driving method of a shift register unit, the shift register unit including an input circuit, coupled to a voltage stabilizer node and an input signal terminal of the shift register unit, and configured to receive an input signal from the input signal terminal and output the input signal to the voltage stabilizer node;

• a voltage-stabilizing circuit, coupled to the voltage stabilizer node and a pull-up node of the shift register unit, and configured to input potential of the voltage stabilizer node to the pull-up node and control potential of the voltage stabilizer node;
• an output circuit, coupled to the pull-up node and a clock signal terminal and an output signal terminal of the shift register unit, and configured to receive a clock signal from the clock signal terminal, and provide an output signal to the output signal terminal based on the clock signal received under control of the potential of the pull-up node;
• and a control circuit, coupled to the pull-up node and the output signal terminal, and configured to control potential of the output signal terminal under control of the potential of the pull-up node;
• wherein the voltage-stabilizing circuit comprises:
• a first transistor having a gate and a first electrode coupled together, and a second electrode coupled to the pull-up node;
• and a second transistor having a gate coupled to the pull-up node and a first electrode coupled to a first power signal terminal;
• wherein the driving method comprises:
• in a first period, applying an input signal at a first level to an input signal terminal, wherein the input signal at the first level is output to a voltage stabilizer node by an input circuit, and potential of the voltage stabilizer node is input to a pull-up node by a voltage-stabilizing circuit;
• in a second period, applying an input signal at a second level to the input signal terminal, wherein potential of the pull-up node causes an output circuit to provide a clock signal of a clock signal terminal to an output signal terminal;
• and
• in a third period, applying a reset signal at the first level to a reset signal terminal of the shift register unit to reset the pull-up node, wherein the potential of the pull-up node causes a control circuit to pull down the output signal terminal to the second level,
• wherein, in the first period and the second period, the potential of the pull-up node causes the voltage-stabilizing circuit to control potential of the voltage stabilizer node within a preset range.