Scan driver and display device
AssigneeSamsung Display Co., Ltd.
InventorHyun Joon Kim
Life of this patent
Estimating the term…
Abstract
A scan driver includes stages, each of the stages receiving first and second clock signals having a first low level as an active level, and a third clock signal having a high level as the active level. Each of the stages includes a logic circuit that changes a voltage of a first node to the first low level based on an input signal and the first clock signal, and changes a voltage of the first node to a second low level lower than the first low level based on the second clock signal, a first output buffer that outputs, as an active-low scan signal, the second clock signal in response to the voltage of the first node, and a second output buffer that outputs, as an active-high scan signal, the third clock signal in response to the voltage of the first node.
Claims20
A scan driver comprising:
- a plurality of stages receiving a first clock signal, a second clock signal and a third clock signal, each of the plurality of stages comprising:
- a logic circuit that changes a voltage of a first node to a first low level based on an input signal and the first clock signal, and changes the voltage of the first node to a second low level based on the second clock signal, a voltage level of the second low level being lower than a voltage level of the first low level;
- a first output buffer that outputs a first output signal in synchronization with the second clock signal based on the voltage of the first node;
- and
- a second output buffer that outputs a second output signal in synchronization with the third clock signal based on the voltage of the first node,
- wherein a low period of the third clock signal at least partially overlaps a low period of the second clock signal.
A scan driver including a plurality of stages, each of the plurality of stages comprising:
- a first transistor including a gate receiving a first clock signal, a first terminal receiving an input signal, and a second terminal electrically connected to a third node;
- a seventh transistor including a gate receiving a low gate voltage, a first terminal electrically connected to the third node, and a second terminal electrically connected to a first node;
- a first capacitor including a first electrode electrically connected to a first output node, and a second electrode electrically connected to the first node;
- an eighth transistor including a gate electrically connected to the first node, a first terminal electrically connected to the first output node, and a second terminal receiving a second clock signal;
- a ninth transistor including a gate electrically connected to a second node, a first terminal receiving a high gate voltage, and a second terminal electrically connected to the first output node;
- a tenth transistor including a gate electrically connected to the first node, a first terminal electrically connected to a second output node, and a second terminal receiving a third clock signal;
- and
- an eleventh transistor including a gate electrically connected to the second node, a first terminal receiving the low gate voltage, and a second terminal electrically connected to the second output node.
A display device comprising:
- a display panel including a plurality of pixels;
- a data driver that provides data signals to the plurality of pixels;
- a scan driver that provides first output signals and second output signals to the plurality of pixels;
- and
- a controller that controls the data driver and the scan driver,
- wherein the scan driver includes a plurality of stages receiving a first clock signal, a second clock signal and a third clock signal, each of the plurality of stages comprising:
- a logic circuit that changes a voltage of a first node to a first low level based on an input signal and the first clock signal, and changes the voltage of the first node to a second low level based on the second clock signal, a voltage level of the second low level being lower than a voltage level of the first low level;
- a first output buffer that outputs a corresponding one of the first output signals in synchronization with the second clock signal based on the voltage of the first node;
- and
- a second output buffer that outputs a corresponding one of the second output signals in synchronization with the third clock signal based on the voltage of the first node,
- wherein a low period of the third clock signal at least partially overlaps a low period of the second clock signal.
Dependencies are inferred from the claim text.