Scan driver circuitry and operating method thereof

A scan driver circuit for an active matrix array, wherein the scan driver circuit comprises a plurality of stages,

• wherein a plurality of decoder signals are used in each of the plural stages, and the scan driver circuit comprises a plurality of decoders that are sequentially driven at different driving timings in the same stage based on a combination of the plural decoder signals or that are driven at the same timing in different stages,
• wherein a last decoder of the plural decoders sequentially outputs a scan line signal according to a driving state of the plural decoders in each of the plural stages,
• wherein the combination of plural decoder signals comprises at least one of a first combination,
• wherein first and second decoder signals among the plural decoder signals indicate a low state, a second combination wherein the first decoder signal indicates a low state and the second decoder signal indicates a high state, a third combination,
• wherein the first decoder signal indicates a high state and the second decoder signal indicates a low state, and a fourth combination wherein the first aid second decoder signals indicate a high state,
• wherein a first decoder of a first stage among the plural stages is selectively driven when a decoder signal of the first combination is initially applied, and
• wherein the second decoder of the first stage among the plural stages and the first decoder of the second stage among the plural stages are selectively driven when the decoder signal of the first combination is applied secondarily.

A method of driving a scan driver circuit for an active matrix array, wherein the scan driver circuit comprises a plurality of stages,

• the method comprising:
• driving sequentially a plurality of decoders at different driving timings based on a combination of a plurality of decoder signals in each of the plural stages;
• driving a plurality of decoders at the same timing based on a combination of the plural decoder signals in different stages among the plural stages;
• and
• outputting sequentially scan line signals according to a driving state of the plural decoders in a last decoder among the plural decoders,
• wherein each of the plural decoders comprises an input part, an output part and a reset part, and
• wherein the input pan comprises a first decoding transistor and a fourth decoding transistor connected to a clock signal;
• and second, third, fifth and sixth decoding transistors that are connected in series to each of the first decoding transistor and the fourth decoding transistor and that are connected to the plural decoder signals.