Quantum data loader
AssigneeQC Ware Corp.
InventorIordanis Kerenidis
Life of this patent
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Abstract
This disclosure relates generally to the field of quantum algorithms and quantum data loading, and more particularly to constructing quantum circuits for loading classical data into quantum states which reduces the computational resources of the circuit, e.g., number of qubits, depth of quantum circuit, and type of gates in the circuit.
Claims20
A quantum circuit for use in encoding an n-dimensional vector representing classical data into quantum states, the quantum circuit comprising:
- a first group of √n qubits and a second group of √n qubits;
- a first layer comprising a first X gate applied to a qubit in the first group and a second X gate applied to a qubit in the second group;
- a first plurality of subsequent layers that applies BS gates to the first group of qubits according to a binary tree pattern, wherein each BS gate is a single parametrized 2-qubit gate;
- and
- a second plurality of subsequent layers that applies controlled BS gates (c-BS gates) to qubits in the first and second groups, wherein each c-BS gate applies a BS gate to qubits in the second group and is controlled by a qubit in the first group,
- wherein a number of layers is not more than ceiling(√n log2(n)).
A non-transitory computer-readable storage medium comprising stored instructions to execute a quantum circuit by a quantum computer, the quantum computer comprising a first group of √{square root over (n)} qubits and a second group of √{square root over (n)} qubits, the stored instructions, when executed by the quantum computer, cause the quantum computer to perform operations comprising:
- executing a first layer of quantum gates, wherein executing the first layer comprises applying a first X gate to a qubit in the first group and applying a second X gate to a qubit in the second group;
- executing a first plurality of subsequent layers of quantum gates, wherein executing the first plurality of subsequent layers comprises applying BS gates to the first group of qubits according to a binary tree pattern, wherein each BS gate is a single parametrized 2-qubit gate;
- and
- executing a second plurality of subsequent layers of quantum gates, wherein executing the second plurality of subsequent layers comprises applying controlled BS gates (c-BS gates) to qubits in the first and second groups, wherein each c-BS gate applies a BS gate to qubits in the second group and is controlled by a qubit in the first group,
- wherein a number of layers is not more than ceiling(√{square root over (n)} log 2(n)).
A method for executing a quantum circuit by a quantum computer, the quantum computer comprising a first group of √{square root over (n)} qubits and a second group of √{square root over (n)} qubits, the method comprising:
- executing a first layer of quantum gates, wherein executing the first layer comprises applying a first X gate to a qubit in the first group and applying a second X gate to a qubit in the second group;
- executing a first plurality of subsequent layers of quantum gates, wherein executing the first plurality of subsequent layers comprises applying BS gates to the first group of qubits according to a binary tree pattern, wherein each BS gate is a single parametrized 2-qubit gate;
- and
- executing a second plurality of subsequent layers of quantum gates, wherein executing the second plurality of subsequent layers comprises applying controlled BS gates (c-BS gates) to qubits in the first and second groups, wherein each c-BS gate applies a BS gate to qubits in the second group and is controlled by a qubit in the first group,
- wherein a number of layers is not more than ceiling(√{square root over (n)} log2(n)).
Dependencies are inferred from the claim text.