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US 11,694,016 B2Granted
Fast topology bus router for interconnect planning
AssigneeSynopsys, Inc.
InventorsZhengtao Yu, Balkrishna Rashingkar, David Peart, Douglas Chang, Yiding Han
Life of this patent
Estimating the term…
Abstract
A method includes receiving a netlist for a chip including a bus and determining, by one or more processors and based on the netlist, a first routing topology for the bus and through a routing region of the chip by comparing a demand of the bus to a capacity of a plurality of cells of the routing region. The method also includes generating a layout for the chip based on the first routing topology.
Claims17
A method comprising:
- receiving a netlist for a chip comprising a bus;
- determining, by one or more processors and based on the netlist, a first routing topology for the bus and through a routing region of the chip by a process comprising comparing a first demand of a first portion of the bus to a capacity of a first cell of the routing region and comparing a second demand of a second portion of the bus to a capacity of a second cell of the routing region, wherein the first cell is adjacent to the second cell in the routing region;
- and
- generating a layout for the chip based on the first routing topology.
1 more element
An apparatus comprising:
- a memory;
- and
- a hardware processor communicatively coupled to the memory, the hardware processor configured to:
- receive a netlist for a chip comprising a bus;
- determine, based on the netlist, a first routing topology for the bus and through a routing region of the chip by a process comprising comparing a first demand of a first portion of the bus to a capacity of a first cell of the routing region and comparing a second demand of a second portion of the bus to a capacity of a second cell of the routing region, wherein the first cell is adjacent to the second cell in the routing region;
- and
- generate a layout for the chip based on the first routing topology.
4 more elements
Dependencies are inferred from the claim text.